畢業(yè)設計外文資料翻譯---ad561芯片的介紹與應用

1、<p>　　畢業(yè)設計(論文)外文資料翻譯</p><p>　　系： 電子工程與光電技術系 </p><p>　　專 業(yè)： 通信工程 </p><p>　　姓 名： </p><

2、p>　　學 號： 070404157 </p><p>　　外文出處： Analog Devices </p><p>　　附 件： 1.外文資料翻譯譯文；2.外文原文。 </p><p>　　注：請將該封面與附件裝訂成冊。</p><p&

3、gt;　　附件1：外文資料翻譯譯文</p><p>　　AD561芯片的介紹與應用</p><p>　　AD561是一款集成了10位數(shù)模轉(zhuǎn)換器和高穩(wěn)定電壓轉(zhuǎn)換器的芯片。使用10個高精密電流控制開關，控制放大器，引用電壓和激光微調(diào)薄膜硅鉻電阻網(wǎng)絡，該設備生產(chǎn)一種快速、精確的模擬輸出電流。激光微調(diào)電阻器的應用快速而準確，穩(wěn)定的電流到電壓的轉(zhuǎn)換，它們的精度可以達到0.1%。從而在許多情況下消除外

4、部剪切。</p><p>　　幾個主要技術結(jié)合起來，使AD561提供最精確和最穩(wěn)定的10位DAC。低溫度系數(shù)，高穩(wěn)定性的薄膜網(wǎng)絡在晶圓級微調(diào)高分辨率激光系統(tǒng)0.01％的典型的線性關系。</p><p>　　【AD561產(chǎn)品說明】</p><p>　　AD561 還包含一個低噪音、 高穩(wěn)定性的穩(wěn)壓二極管生產(chǎn)參考電壓與較好的長期穩(wěn)定性和挑戰(zhàn)最離散穩(wěn)壓引用的溫度周期特點。

5、允許自定義的每個設備的溫度系數(shù)校正激光裁剪溫度補償電路。這將導致 15 ppm/°C / ° C ； 一個典型的全面溫度系數(shù)TC 是測試和保證 30 ppm / ° C 最大值為 K 和 T 版本、 60 ppm/°C / ° C 最大 S，和 80 ppm / ° C 。</p><p>　　該AD561可在四個性能等級。該AD561J和K，并指明了在

6、0 ° C至+70 ° C使用溫度范圍，并在一個16引腳密封陶瓷撥用或16引腳塑料DIP成型。和T級的AD561S指定為-55 ° C至+125 ° C范圍內(nèi)，并在陶瓷封裝。</p><p><b>　　【特征】</b></p><p><b>　　功能框圖</b></p><p>

7、　　總電流輸出轉(zhuǎn)換器 高穩(wěn)定性掩埋穩(wěn)壓二極管參考 激光修整，精度高（1 / 4 LSB最大錯誤， AD561K，T）邊輸出為0 V至+10 V的應用電阻器，65 V輸入快速設置- 250毫微秒到1 / 2 LSB保證在整個工作的單調(diào)性溫度范圍TTL/晶體管邏輯和CMOS兼容（正真邏輯）單芯片單片建設可用于片式結(jié)構(gòu)兼容信息產(chǎn)業(yè)部- ST

8、D - 883標準。 </p><p>　　[1]【AD561產(chǎn)品薈萃】</p><p>　　1、先進的加工和激光在單片晶圓級微調(diào)作出了AD561最準確的10位轉(zhuǎn)換器使用，同時，用大量的集成電路生產(chǎn)成本相一致。該AD561K和T有1 / 4 LSB的最大相對精度和1 / 2 LSB的最大微分非線性。低班的R - 2R梯形保證所有AD561單位將在整個單調(diào)工作溫度范圍。</p>

9、<p>　　2、數(shù)字系統(tǒng)的接口，簡化了一種積極的真正標準二進制代碼的使用。數(shù)字輸入電壓閾值起到供應水平的積極作用；連接到VCC的數(shù)字邏輯電源自動設置閾值邏輯系列為正在使用的適當水平。邏輯吸收電流的要求是只有25毫安。</p><p>　　3、當前的高速開關設計轉(zhuǎn)向定居在不到250納秒，最壞的情況下數(shù)字代碼轉(zhuǎn)換納秒。 這允許逐次逼近結(jié)構(gòu)A / D轉(zhuǎn)換在3毫秒轉(zhuǎn)換器，以5毫秒的范圍。</p>

10、<p>　　4、該AD561有一個輸出電壓合格范圍-2 V至+10 V的，可直接電流到電壓的轉(zhuǎn)換只有一個輸出電阻，省略了運算放大器。結(jié)果由于輸出漏電流40兆瓦集電極開路輸出阻抗誤差可以忽略不計。 </p><p>　　5、該AD561是兼容的版本與MILSTD可供883。參照ADI公司軍工產(chǎn)品數(shù)據(jù)手冊或電流AD561/883B詳細數(shù)據(jù)表規(guī)格。</p><p>　　[2]【AD5

11、61的分析和應用】</p><p>　　AD561提供整個溫度范圍內(nèi)真正的10位分辨率</p><p>　　精度：ADI公司定義為最大精度差的實際，調(diào)整DAC輸出從理想的模擬輸出（0直線繪制的FS – 升LSB）的任何位組合。該AD561是激光修整，以 1 / 4的LSB（FS的0.025％），最大誤差在25℃下的K 和T版本 - 1 / 2的J和S的LSB。</p><

12、;p>　　單調(diào)性：一個DAC被認為是單調(diào)的，如果輸出無論是增加或保持不變，增加數(shù)字輸入這樣，輸出將始終是一個單值函數(shù)輸入。所有版本的AD561是在其整個單調(diào)工作溫度范圍。</p><p>　　微分非線性：單調(diào)的行為要求微分非線性誤差小于1 LSB的同時在+25 ° C以上的溫度范圍興趣。微分非線性是衡量的變異在模擬值，歸一化到全面，具有相關聯(lián)的1 LSB的變化，數(shù)字輸入碼。例如，對于一個10伏滿量

13、程輸出，1個LSB數(shù)字輸入碼變化應結(jié)果在9.8 mV的模擬輸出的變化（1個LSB = 10伏'1 / 1024 = 9.8毫伏）。如果在實際使用中，然而，1 LSB的變化在一個只有2.45毫伏的變化（1 / 4 LSB）的輸入碼結(jié)果在模擬輸出，差分非線性誤差將7.35毫伏，或3 / 4 LSB的。</p><p>　　微分非線性溫度系數(shù)也必須如果設備被認為是保持了全面單調(diào)工作溫度范圍。一個微分非線性溫度百

14、萬分之2.5系數(shù)/ ° C 能，在最壞條件下為+25 ° C的溫度變化至+125 ° C，添加0.025％（2.5百萬分之100 3 /錯誤℃）。由此產(chǎn)生的誤差然后可以高達0.025％+ 0.025％= 0.05％的FS（1 / 2 LSB代表FS的0.05％）。為了準確確定所有版本的性能，因此在AD561進行了測試，100％是單調(diào)整個工作溫度范圍。</p><p>　　緩沖電壓的連

15、接的AD561輸出 </p><p>　　標準電流電壓轉(zhuǎn)換連接使用運算放大器在這里顯示與首選修剪技術。如果一個低失調(diào)運算放大器（AD510，AD741L，AD301AL）時，性能優(yōu)良可在許多情況下沒有修整。 （一個5毫伏運算放大器的偏移量相當于1 / 2 LSB的規(guī)模在10伏。）如果一25瓦固定電阻代替50瓦的微調(diào)，單極零通常會在± 1 / 10的LSB（加運算放大器偏移），和滿度精度將在±

16、1 LSB的。</p><p>　　推薦的AD509緩沖電壓輸出應用，需要一個穩(wěn)定時間為± 1 / 2 LSB的一微秒。反饋電容顯示與每項申請的最佳值，這需要電容25皮法的補償DAC輸出電容。</p><p>　　單極配置 這種配置，如圖2所示，將提供一個單極0 V至+10 V的輸出范圍。 步驟1…調(diào)零 將所有位關和調(diào)整，直到運算放大器微調(diào)中，R1，輸出讀取0.000伏（1

17、個LSB = 9.76毫伏）。 步驟2…增益調(diào)節(jié) 將所有位的開和調(diào)整，直到50瓦增益微調(diào)，R2中，輸出為9.990伏特。 （滿刻度調(diào)整到小于1個LSB額定滿規(guī)模10.000伏。如果10.23 V滿刻度）是理想 （正好10毫伏/位），插入一個120 W的電阻與R2串聯(lián)。</p><p>　　雙極型配置 這種配置，如圖3所示，將提供一個兩極輸出電壓從-5.000到4.990伏，具有正全面與ON（全為1）所有位

18、發(fā)生。</p><p>　　第1步…調(diào)零 只接通MSB，關閉所有其他位。微調(diào)整R3的50瓦，給予0.000輸出電壓。為了獲得最大的分辨率，一個120瓦的電阻可以被放置在與R3并聯(lián)。 步驟2…增益調(diào)節(jié) 關閉所有的位，50瓦的增益調(diào)整電位器給-5.000伏讀。 請注意，這是沒有必要削減運算放大器獲得全面準確度在室溫下。在大多數(shù)情況下雙極，運算放大器的微調(diào)是不必要的，除非運算放大器的修剪偏移過大。</p&

19、gt;<p>　　±10伏雙極輸出緩沖該AD561也可以連接，±10伏雙極性范圍有一個額外的外部電阻，圖4所示，一較大的值微調(diào)需要寬容補償薄膜電阻器，這是修剪，以配合全面電流。為獲得最佳滿量程溫度系數(shù)的表現(xiàn)，外部電阻應該有一個TC-50百萬分之/℃。</p><p>　　圖2.0 V至+10 V單極性電壓輸出</p><p>　　圖3.±5V的

20、雙極性電壓輸出緩沖</p><p>　　圖4.±10 V的電壓輸出緩沖</p><p>　　圖5.參考線路圖顯示，控制放大器，開關單元，R - 2R梯形，和位安排對AD561</p><p>　　電路描述一個簡化原理圖與電路的基本特點 AD561是如圖5所示。參考電壓，CR1的，是一個埋齊納（或地下?lián)舸┒O管）。這種器件具有更好的全能比NPN管b

21、aseemitter反向擊穿二極管（表面齊納）性能，</p><p>　　這是在幾乎普遍使用集成電路的電壓作為參考。大大提高了長期穩(wěn)定性和低噪聲是從孤立的掩埋齊納派生的主要好處從表面應力崩潰點和移動氧化物電荷影響。 7.5伏的額定設備（包括溫度補償電路）是由一個電流源的所以正電源負電源可以被允許下降，因為低至4.5伏。每個二極管的溫度系數(shù)單獨確定;此數(shù)據(jù)，然后用于激光修剪補償電路，以平衡整體TC到零。該結(jié)果TC是

22、典型的0至±為15 ppm /° C的負參考水平倒格A1和規(guī)模給予2.5伏參考，它可以由低正電源。在AD561，在16引腳封裝的撥，有2.5伏的基準（REF輸出）直接連接到放大器的輸入端的控制（文獻中）。緩沖的引用不是直接可用除了通過外部2.5千瓦雙極電阻抵消。2.5千瓦縮放電阻和控制放大器A2強制1 mA的參考電流流過晶體管Q1的參考，其中有一個相對的8A條發(fā)射區(qū)。這是通過迫使梯子底部的正常電壓。由于Q1和Q2的發(fā)

23、射極地區(qū)有平等和平等5千瓦發(fā)射極電阻，Q2還攜帶1毫安。梯子約束Q7的電壓降（與第4A區(qū)）開展僅0.5毫安;Q8攜帶0.25毫安等。前四個顯著的位單元的發(fā)射是完全縮放區(qū)，以配合最佳VBE和第一季度的VBE漂移比賽，以及為測試比賽。這些影響</p><p>　　在Q3，Q4，Q5和Q6旨在引導切換細胞的細胞目前無論是地面（1位低）或DAC輸出（第1位高）。整個轉(zhuǎn)換單元進行相同的電流是否位或關閉時，盡量減少和地熱瞬態(tài)

24、電流誤差。邏輯閾值，這是產(chǎn)生從正電源（數(shù)字邏輯接口），適用于每一個細胞的一面。</p><p>　　數(shù)字邏輯接口所有標準的接口，積極提供邏輯很容易與在AD561。數(shù)字是正真正的二進制代碼（所有位高，邏輯“1“，給正滿量程輸出）。邏輯輸入負荷因子（100 nA的最大邏輯“1”，在邏輯-25 mA最大“0”3 pF的電容），低于一數(shù)字相當于所有負載邏輯的家庭，包括無緩沖的CMOS。數(shù)字閾值設置內(nèi)部作為一個在正電源的

25、功能，如如圖6所示。對于大多數(shù)應用程序，連接到VCC的正邏輯供應量將在適當?shù)募墑e設置的閾值最大噪聲免疫力。對于非標準的應用，請參考圖6的最低值。</p><p>　　未提交位輸入線將承擔起一個“1“狀態(tài)（類似于為TTL），但他們是高阻抗和受雜音。未使用的數(shù)字輸入應直接連接到地或VCC，應有的作用。</p><p>　　圖6.數(shù)字化閾值隨正電源</p><p><

26、;b>　　附件2：外文原文</b></p><p>　　Introduction and Application of AD561 CHIP</p><p>　　The AD561 is an integrated circuit 10-bit digital-to-analog converter combined with a high stability volta

27、ge reference fabricated on a single monolithic chip. Using ten precision highspeed current-steering switches, a control amplifier, voltage reference, and laser-trimmed thin-film SiCr resistor network, the device produces

28、 a fast, accurate analog output current.Laser trimmed output application resistors are also included to</p><p>　　facilitate accurate, stable current-to-voltage conversion; they are trimmed to 0.1% accuracy,

29、thus eliminating external trimmers in many situations.</p><p>　　Several important technologies combine to make the AD561 the most accurate and most stable 10-bit DAC available. The low temperature coefficien

30、t, high stability thin-film network is trimmed at the wafer level by a fine resolution laser system to 0.01% typical linearity. This results in an accuracy specification of ±1/4 LSB max for the K and T versions, and

31、 1/2 LSB max for the J and S versions.</p><p>　　【AD561 PRODUCT DESCRIPTION】 </p><p>　　The AD561 also incorporates a low noise, high stability subsurface zener diode to produce a reference voltag

32、e with excellent long term stability and temperature cycle characteristics, which challenge the best discrete Zener references. A temperature compensation circuit is laser-trimmed to allow</p><p>　　custom co

33、rrection of the temperature coefficient of each device. This results in a typical full-scale temperature coefficient of 15 ppm/°C; the TC is tested and guaranteed to 30 ppm/°C max for the K and T versions, 60 p

34、pm/°C max for the S, and 80 ppm/°C for the J.</p><p>　　The AD561 is available in four performance grades. The AD561J and K are specified for use over the 0°C to +70°C temperature range an

35、d are available in either a 16-pin hermetically-sealed ceramic DIP or a 16-pin molded plastic</p><p>　　DIP. The AD561S and T grades are specified for the –55°C to +125°C range and are available in

36、the ceramic package. </p><p>　　【FEATURES】 </p><p>　　FUNCTIONAL BLOCK DIAGRAM</p><p>　　Complete Current Output Converter</p><p>　　High Stability Buried Zener Reference&l

37、t;/p><p>　　Laser Trimmed to High Accuracy (1/4 LSB Max Error,</p><p>　　AD561K, T)</p><p>　　Trimmed Output Application Resistors for 0 V to +10 V,</p><p>　　65 V Ranges</

38、p><p>　　Fast Settling – 250 ns to 1/2 LSB</p><p>　　Guaranteed Monotonicity Over Full Operating</p><p>　　Temperature Range</p><p>　　TTL/DTL and CMOS Compatible (Positive Tr

39、ue Logic)</p><p>　　Single Chip Monolithic Construction</p><p>　　Available in Chip Form</p><p>　　MlL-STD-883-Compliant Versions Available</p><p>　　【1】【AD561 PRODUCT HIGH

40、LIGHTS】 </p><p>　　1. Advanced monolithic processing and laser trimming at the wafer level have made the AD561 the most accurate 10-bit converter available, while keeping costs consistent with large volume in

41、tegrated circuit production. The AD561K and T have 1/4 LSB max relative accuracy and 1/2 LSB max differential nonlinearity. The low TC R-2R ladder guarantees that all AD561 units will be monotonic over the entire operati

42、ng temperature range.</p><p>　　2. Digital system interfacing is simplified by the use of a positive true straight binary code. The digital input voltage threshold is a function of the positive supply level;

43、connecting VCC to the digital logic supply automatically sets the threshold to the proper level for the logic family being used. Logic sink current requirement is only 25 mA.</p><p>　　3. The high speed curre

44、nt steering switches are designed to settle in less than 250 ns for the worst case digital code transition. This allows construction of successive-approximation A/D converters in the 3 ms to 5 ms range.</p><p&

45、gt;　　4. The AD561 has an output voltage compliance range from –2 V to +10 V, allowing direct current-to-voltage conversion with just an output resistor, omitting the op amp. The 40 MW open collector output impedance resu

46、lts in negligible errors due to output leakage currents.</p><p>　　5. The AD561 is available in versions compliant with MILSTD-883. Refer to the Analog Devices Military Products Databook or current AD561/883B

47、 data sheet for detailed specifications.</p><p>　　【2】【Analysis and Application of AD561】</p><p>　　THE AD561 OFFERS TRUE 10-BIT RESOLUTION OVER FULL TEMPERATURE RANGE</p><p>　　Accura

48、cy: Analog Devices defines accuracy as the maximum deviation of the actual, adjusted DAC output (see page 5) from the ideal analog output (a straight line drawn from 0 to FS – lLSB) for any bit combination. The AD561 is

49、laser trimmed to 1/4 LSB (0.025% of FS) maximum error at +25°C for the K and T versions – 1/2 LSB for the J and S.</p><p>　　Monotonicity: A DAC is said to be monotonic if the output either increases or

50、remains constant for increasing digital inputs such that the output will always be a single-valued function of the input. All versions of the AD561 are monotonic over their full operating temperature range.</p>&l

51、t;p>　　Differential Nonlinearity: Monotonic behavior requires that the differential nonlinearity error be less than 1 LSB both at +25°C and over the temperature range of interest. Differential nonlinearity is the

52、measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. For example, for a 10 volt full scale output, a change of 1 LSB in digital input code should resul

53、t in a 9.8 mV change in the analog output (1 LSB = 10 V ´ 1/1024 = 9.8 mV)</p><p>　　CONNECTING THE AD561 FOR BUFFERED VOLTAGE OUTPUT</p><p>　　The standard current-to-voltage conversion conn

54、ections using an operational amplifier are shown here with the preferred trimming techniques. If a low offset operational amplifier (AD510, AD741L, AD301AL) is used, excellent performance can be obtained in many situatio

55、ns without trimming. (A 5 mV</p><p>　　op amp offset is equivalent to 1/2 LSB on a 10 volt scale.) If a 25 W fixed resistor is substituted for the 50 W trimmer, unipolar zero will typically be within ±1/

56、10 LSB (plus op amp offset), and full scale accuracy will be within ±1 LSB. Substituting a 25 W resistor for the 50 W bipolar offset trimmer will give a bipolar zero error typically within ±1 LSB. The AD509 is

57、recommended for buffered voltage-output applications that require a settling time to ±1/2 LSB of one microsecond. The feedback</p><p>　　UNIPOLAR CONFIGURATION</p><p>　　This configuration, s

58、hown in Figure 2, will provide a unipolar 0 V to +10 V output range.</p><p>　　STEP I . . . ZERO ADJUST</p><p>　　Turn all bits OFF and adjust op amp trimmer, R1, until the output reads 0.000 volt

59、s (1 LSB = 9.76 mV).</p><p>　　STEP 11. . . GAIN ADJUST</p><p>　　Turn all bits ON and adjust 50 W gain trimmer, R2, until the output is 9.990 volts. (Full scale is adjusted to 1 LSB less than nom

60、inal full scale of 10.000 volts.) If a 10.23 V full scale is desired (exactly 10 mV/bit), insert a 120 W resistor in series with R2.</p><p>　　BIPOLAR CONFIGURATION</p><p>　　This configuration, s

61、hown in Figure 3, will provide a bipolar output voltage from –5.000 to +4.990 volts, with positive full scale occurring with all bits ON (all 1s).</p><p>　　STEP 1. . . ZERO ADJUST</p><p>　　Turn

62、ON MSB only, turn OFF all other bits. Adjust 50 W trimmer R3, to give 0.000 output volts. For maximum resolution a 120 W resistor may be placed in parallel with R3.</p><p>　　STEP 11. . . GAIN ADJUST</p>

63、;<p>　　Turn OFF all bits, adjust 50 W gain trimmer to give a reading of –5.000 volts. </p><p>　　Please note that it is not necessary to trim the op amp to obtain full accuracy at room temperature. In

64、most bipolar situations, the op amp trimmer is unnecessary unless the untrimmed offset drift of the op amp is excessive.</p><p>　　±10 VOLT BUFFERED BIPOLAR OUTPUT</p><p>　　The AD561 can als

65、o be connected for a ±10 volt bipolar range with an additional external resistor as shown in Figure 4. A larger value trimmer is required to compensate for tolerance in the thin film resistors, which are trimmed to

66、match the full-scale current. For best full scale temperature coefficient performance, the external resistors should have a TC of –50 ppm/°C.</p><p>　　Figure 2. 0 V to +10 V Unipolar Voltage Output</

67、p><p>　　Figure 3. ±5 V Buffered Bipolar Voltage Output</p><p>　　Figure 4. ±10 V Buffered Voltage Output</p><p>　　Figure 5. Circuit Diagram Showing Reference, Control Amplifie

68、r, Switching Cell, R-2R Ladder, and Bit Arrangement of AD561</p><p>　　CIRCUIT DESCRIPTION</p><p>　　A simplified schematic with the essential circuit features of the AD561 is shown in Figure 5. T

69、he voltage reference, CR1, is a buried Zener (or subsurface breakdown diode). This device exhibits far better all-around performance than the NPN baseemitter reverse-breakdown diode (surface Zener), which is in nearly un

70、iversal use in integrated circuits as a voltage reference. Greatly improved long-term stability and lower noise are the</p><p>　　major benefits the buried Zener derives from isolating the breakdown point fro

71、m surface stress and mobile oxide charge effects. The nominal 7.5 volt device (including temperature compensation circuitry) is driven by a current source to the negative supply so the positive supply can be allowed to d

72、rop as low as 4.5 volts. The temperature coefficient of each diode is individually determined; this data is then used to laser trim a compensating circuit to balance the overall TC to zero. The typical </p><p&

73、gt;　　OUT) connected directly to the input of the control amplifier (REF IN). The buffered reference is not directly available externally except through the 2.5 kW bipolar offset resistor.</p><p>　　The 2.5 kW

74、 scaling resistor and control amplifier A2 then force a 1 mA reference current to flow through reference transistor Q1, which has a relative emitter area of 8A. This is accomplished by forcing the bottom of the ladder to

75、 the proper voltage. Since Q1 and Q2 have equal emitter areas and equal 5 kW emitter resistors, Q2 also carries 1 mA. The ladder voltage drop constrains Q7 (with area 4A) to carry only 0.5 mA; Q8 carries 0.25 mA, etc. Th

76、e first four significant bit cells are exactly sca</p><p>　　area to match Q1 for optimum VBE and VBE drift match, as well as for beta match. These effects are insignificant for the lower order bits, which ac

77、count for a total of only 1/16 of full scale. However, the 18 mV VBE difference between two matched transistors carrying emitter currents in a ratio of 2:1 must be corrected. This is achieved by forcing 120 mA through th

78、e 150 W interbase resistors. These resistors, and the R-2R ladder resistors, are actively laser-trimmed at the wafer level to bring t</p><p>　　(BIT 1 high). The entire switching cell carries the same current

79、 whether the bit is on or off, minimizing thermal transients and ground current errors. The logic threshold, which is generated from the positive supply (see Digital Logic Interface), is applied to one side of each cell.

80、</p><p>　　DIGITAL LOGIC INTERFACE</p><p>　　All standard positive supply logic families interface easily with the AD561. The digital code is positive true binary (all bits high, Logic “1,” gives

81、positive full scale output). The logic input load factor (100 nA max at Logic “1,” –25 mA max at Logic “0,” 3 pF capacitance), is less than one equivalent digital load for all logic families, including unbuffered CMOS. T