基于單片機(jī)的多點(diǎn)溫度檢測(cè)系統(tǒng)的設(shè)計(jì)外文翻譯

1、<p>　　基于單片機(jī)的多點(diǎn)溫度檢測(cè)系統(tǒng)的設(shè)計(jì)</p><p>　　一、引言　　隨著社會(huì)的發(fā)展和技術(shù)的進(jìn)步，人們?cè)絹碓阶⒅販囟葯z測(cè)與顯示的重要性。溫度檢測(cè)與狀態(tài)顯示技術(shù)與設(shè)備已經(jīng)普遍應(yīng)用于各行各業(yè)，市場(chǎng)上的產(chǎn)品層出不窮。溫度檢測(cè)及顯示也逐漸采用自動(dòng)化控制技術(shù)來實(shí)現(xiàn)監(jiān)控。本課題就是一個(gè)溫度檢測(cè)及狀態(tài)顯示的監(jiān)控系統(tǒng)。二、系統(tǒng)方案　　本系統(tǒng)采用 AT89C51 作為該系統(tǒng)的單片機(jī)。系統(tǒng)整體硬件電路包括

2、，電源電路，傳感器電路，溫度顯示電路，上下限報(bào)警電路等。報(bào)警電路可以在被測(cè)溫度不在上下限范圍內(nèi)時(shí)，發(fā)出報(bào)警鳴叫聲音。溫度控制的基本原理為:當(dāng)DSl8B20 采集到溫度信號(hào)后，將溫度信號(hào)送至AT89C51 中處理，同時(shí)將溫度送到LCD 液晶屏顯示，單片機(jī)根據(jù)初始化設(shè)置的溫度上下限進(jìn)行判斷處理，即如果溫度大于所設(shè)的最高溫度就啟動(dòng)風(fēng)扇降溫;如果溫度小于所設(shè)定的最低溫度就啟動(dòng)報(bào)警裝置。溫度控制器的原理圖三、系統(tǒng)硬件設(shè)計(jì)1.單片機(jī)AT89C5

3、1 的介紹</p><p>　　AT89C51是美國(guó)ATMEL公司生產(chǎn)的低電壓，高性能COMS8位單片機(jī)，片內(nèi)含4Kbytes的可反復(fù)擦寫的只讀程序存儲(chǔ)器（PEROM）和128bytes的隨機(jī)存取數(shù)據(jù)存儲(chǔ)器（RAM），器件采用ATMEL公司的高密度、非易失性存儲(chǔ)技術(shù)生產(chǎn)，兼容標(biāo)準(zhǔn)MCS-51指令系統(tǒng)，片內(nèi)置通用8位中央處理器（CPU）和Flash存儲(chǔ)單元，功能強(qiáng)大AT89C51單片機(jī)可為您提供許多高性價(jià)比的應(yīng)用場(chǎng)

4、合，可靈活應(yīng)用于各種控制領(lǐng)域。</p><p><b>　　主要性能參數(shù)：</b></p><p>　　·與MCS-51產(chǎn)品指令系統(tǒng)完全兼容</p><p>　　·4K字節(jié)可重擦寫Flash閃速存儲(chǔ)器</p><p>　　·1000次擦寫周期</p><p>　　&#

5、183;全靜態(tài)操作：0Hz—24MHz</p><p>　　·三級(jí)加密程序存儲(chǔ)器</p><p>　　·128×8字節(jié)內(nèi)部RAM</p><p>　　·32個(gè)可編程I/O口線</p><p>　　·2個(gè)16位定時(shí)/計(jì)數(shù)器</p><p><b>　　·

6、;6個(gè)中斷源</b></p><p>　　·可編程串行UART通道</p><p>　　·低功耗空閑和掉電模式</p><p><b>　　功能特性概述：</b></p><p>　　AT89C51提供以下標(biāo)準(zhǔn)功能：4K字節(jié)Flash閃速存儲(chǔ)器，128字節(jié)內(nèi)部RAM，32個(gè)I/O口線，兩個(gè)

7、16位定時(shí)/計(jì)數(shù)器，一個(gè)5向量?jī)杉?jí)中斷結(jié)構(gòu)，一個(gè)全雙工串行通信口，片內(nèi)振蕩器及時(shí)鐘電路。同時(shí)，AT89C51可降至0Hz的靜態(tài)邏輯操作，并支持兩種軟件可選的節(jié)電工作模式?？臻e方式停止CPU的工作，但允許RAM，定時(shí)/計(jì)數(shù)器。串行通信口及中斷系統(tǒng)繼續(xù)工作。掉電方式保存RAM中的內(nèi)容，但振蕩器停止工作并禁止其它所有部件工作直到下一個(gè)硬件復(fù)位。</p><p><b>　　引腳功能說明：</b>&

8、lt;/p><p><b>　　·VCC：電源電壓</b></p><p><b>　　·GND：地</b></p><p>　　·P0口：P0口是一組8位漏極開路型雙向I/O口，也即地址/數(shù)據(jù)總線復(fù)用口。作為輸出口用時(shí)，每位能吸收電流的方式驅(qū)動(dòng)8個(gè)TTL邏輯門電路，對(duì)端口寫“1”可作為高阻抗輸入

9、端用。</p><p>　　在訪問外部數(shù)據(jù)存儲(chǔ)器或程序存儲(chǔ)器時(shí)，這組口線分時(shí)轉(zhuǎn)換地址（低8位）和數(shù)據(jù)總線復(fù)用，在訪問期間即或內(nèi)部上拉電阻。</p><p>　　在Flash編程時(shí)，P0口接收指令字節(jié)，而在程序校驗(yàn)時(shí)，輸出指令字節(jié)，校驗(yàn)時(shí)，要求外接上拉電阻。</p><p>　　·P1口：P1是一個(gè)帶有內(nèi)部上拉電阻的8位雙向I/O口，P1的輸出緩沖級(jí)可驅(qū)動(dòng)（

10、吸收或輸出電流）4個(gè)TTL邏輯門電路。對(duì)端口寫“1”，通過內(nèi)部的上拉電阻把端口拉到高電平，此時(shí)可作輸入口。作輸入口使用時(shí)，因?yàn)閮?nèi)部存在上拉電阻，某個(gè)引腳被外部信號(hào)拉低時(shí)會(huì)輸出一個(gè)電流（IIL）。</p><p>　　Flash編程和程序校驗(yàn)期間，P1接收低8位地址。</p><p>　　·P2口：P2是一個(gè)帶有內(nèi)部上拉電阻的8位雙向I/O口，P2的輸出緩沖級(jí)可驅(qū)動(dòng)（吸收或輸出電流

11、）4個(gè)TTL邏輯門電路。對(duì)端口寫“1”，通過內(nèi)部的上拉電阻把端口拉到高電平，此時(shí)可作輸入口。作輸入口使用時(shí)，因?yàn)閮?nèi)部存在上拉電阻，某個(gè)引腳被外部信號(hào)拉低時(shí)會(huì)輸出一個(gè)電流（IIL）。</p><p>　　在訪問外部程序存儲(chǔ)器或16位地址的外部數(shù)據(jù)存儲(chǔ)器（例如執(zhí)行MOVX@DPTR指令）時(shí)，P2口送出高8位地址數(shù)據(jù)。在訪問8位地址的外部數(shù)據(jù)存儲(chǔ)器（如執(zhí)行MOVX@RI指令）時(shí)，P2口線上的內(nèi)容在整個(gè)訪問期間不改變。&

12、lt;/p><p>　　Flash編程或檢驗(yàn)時(shí)，P2亦接收高位地址和其它控制信號(hào)。</p><p>　　·P3口：P3口是一組帶有內(nèi)部上拉電阻的8位雙向I/O口。P3口輸出緩沖級(jí)可驅(qū)動(dòng)（吸收或輸出電流）4個(gè)TTL邏輯門電路。對(duì)P3口寫入“1”時(shí)，它們被內(nèi)部上拉電阻拉高并可作為輸入端口。作輸入端時(shí)，被外部拉低的P3口將用上拉電阻輸出電流（IIL）。</p><p&g

13、t;　　P3口還接收一些用于Flash閃速存儲(chǔ)器編程和程序校驗(yàn)的控制信號(hào)。</p><p>　　·RET：復(fù)位輸入。當(dāng)振蕩器工作時(shí)，RET引腳出現(xiàn)兩個(gè)機(jī)器周期以上高電平將使單片機(jī)復(fù)位。</p><p>　　·ALE/：當(dāng)訪問外部程序存儲(chǔ)器或數(shù)據(jù)存儲(chǔ)器時(shí)，ALE（地址鎖存允許）輸出脈沖用于鎖存地址的低8位字節(jié)。對(duì)Flash存儲(chǔ)器編程期間，該引腳還用于輸入編程脈沖（）。即使

14、不訪問外部存儲(chǔ)器，ALE仍以時(shí)鐘振蕩頻率的1/6輸出固定的正脈沖信號(hào)，因此它可對(duì)外輸出時(shí)鐘或用于定時(shí)目的。要注意的是：每當(dāng)訪問外部數(shù)據(jù)存儲(chǔ)器時(shí)將跳過一個(gè)ALE脈沖。</p><p>　　如有必要，可通過對(duì)特殊功能寄存器（SFR）區(qū)中的8EH單元的D0位置位，可禁止ALE操作。該位置位后，只有一條MOVX和MOVC指令A(yù)LE才會(huì)被激活。此外，該引腳會(huì)被微弱拉高，單片機(jī)執(zhí)行外部程序時(shí)，應(yīng)設(shè)置ALE無效。</p&

15、gt;<p>　　·：程序儲(chǔ)存允許（）輸出是外部程序存儲(chǔ)器的讀選通信號(hào)，當(dāng)AT89C51由外部程序存儲(chǔ)器取指令（或數(shù)據(jù)）時(shí)，每個(gè)機(jī)器周期兩次有效，即輸出兩個(gè)脈沖。在此期間，當(dāng)訪問外部數(shù)據(jù)存儲(chǔ)器，這兩次有效的信號(hào)不出現(xiàn)。</p><p>　　EA/VPP：外部訪問允許。欲使CPU僅訪問外部程序存儲(chǔ)器（地址為0000H—FFFFH），EA端必須保持低電平（接地）。需注意的是：如果加密位LB1被

16、編程，復(fù)位時(shí)內(nèi)部會(huì)鎖存EA端狀態(tài)。如EA端為高電平（接VCC端），CPU則執(zhí)行內(nèi)部程序存儲(chǔ)器中的指令。</p><p>　　Flash存儲(chǔ)器編程時(shí)，該引腳加上+12V的編程允許電源VPP，當(dāng)然這必須是該器件是使用12V編程電壓VPP。</p><p>　　XTAL1：振蕩器反相放大器及內(nèi)部時(shí)鐘發(fā)生器的輸入端。</p><p>　　XTAL2：振蕩器反相放大器的輸出端

17、。</p><p>　　Ready/：字節(jié)編程的進(jìn)度可通過RDY/輸出信號(hào)監(jiān)測(cè)，編程期間，ALE變?yōu)楦唠娖健癏”后P3.4（RDY/）端電平被拉低，表示正在編程狀態(tài)（忙狀態(tài)）。編程完成后，P3.4變?yōu)楦唠娖奖硎緶?zhǔn)備就緒狀態(tài)。</p><p><b>　　時(shí)鐘振蕩器：</b></p><p>　　AT89C51中有一個(gè)用于構(gòu)成內(nèi)部振蕩器的高增益反

18、相放大器，引腳XTAL1和XTAL2分別是該放大器的輸入端和輸出端。這個(gè)放大器與作為反饋元件的片外石英晶體 或陶瓷諧振器一起構(gòu)成自激振蕩器。</p><p>　　用戶也可以采用外部時(shí)鐘。這種情況下，外部時(shí)鐘脈沖接到XTAL1端，即內(nèi)部時(shí)鐘發(fā)生器的輸入端，XTAL2則懸空。</p><p>　　由于外部時(shí)鐘信號(hào)是通過一個(gè)2分頻觸發(fā)器后作為內(nèi)部時(shí)鐘信號(hào)的，所以對(duì)外部時(shí)鐘信號(hào)的占空比沒有特殊要求

19、，但最小高電平持續(xù)時(shí)間和最大的低電平持續(xù)時(shí)間應(yīng)符合產(chǎn)品技術(shù)條件的要求。</p><p><b>　　空閑節(jié)電模式：</b></p><p>　　在空閑工作模式狀態(tài)，CPU保持睡眠狀態(tài)而所有片內(nèi)的外設(shè)仍保持激活狀態(tài)，這種方式由軟件產(chǎn)生。此時(shí)，片內(nèi)RAM和所有特殊功能寄存器的內(nèi)容保持不變?？臻e模式可由任何允許的中斷請(qǐng)求或硬件復(fù)位終止。</p><p&g

20、t;　　通過硬件復(fù)位也可將空閑工作模式終止。需要注意的是：當(dāng)由硬件復(fù)位來終止空閑工作模式時(shí)，CPU通常是從激活空閑模式那條指令的下一條指令開始繼續(xù)執(zhí)行程序的，要完成內(nèi)部復(fù)位操作，硬件復(fù)位脈沖要保持兩個(gè)機(jī)器周期有效，在這種情況下，內(nèi)部禁止CPU訪問片內(nèi)RAM，而允許訪問其它端口。為了避免可能對(duì)端口產(chǎn)生意外寫入，激活空閑模式的那條指令后一條指令不應(yīng)是一條對(duì)端口或外部存儲(chǔ)器的寫入指令。</p><p><b>

21、;　　掉電模式：</b></p><p>　　在掉電模式下，振蕩器停止工作，進(jìn)入掉電模式的指令是最后一條被執(zhí)行的指令，片內(nèi)RAM和特殊功能寄存器的內(nèi)容在終止掉電模式前被凍結(jié)。退出掉電模式的唯一方法是硬件復(fù)位，復(fù)位后將重新定義全部特殊功能寄存器但不改變RAM中的內(nèi)容，在VCC恢復(fù)到正常工作電平前，復(fù)位應(yīng)無效，且必須保持一定時(shí)間以使振蕩器重啟動(dòng)并穩(wěn)定工作。</p><p><

22、b>　　程序存儲(chǔ)器的加密：</b></p><p>　　當(dāng)加密位LB1被編程時(shí)，在復(fù)位期間，EA端的邏輯電平被采樣并鎖存，如果單片機(jī)上電后一直沒有復(fù)位，則鎖存起的初始值是一個(gè)隨機(jī)數(shù)，且這個(gè)隨機(jī)數(shù)會(huì)一直保存到真正復(fù)位為止。為使單片機(jī)能正常工作，被鎖存的EA電平值必須與該引腳當(dāng)前的邏輯電平一致。此外，加密位只能通過整片擦除的方法清除。</p><p>　　Flash閃速存儲(chǔ)器

23、的編程：</p><p>　　AT89C51單片機(jī)內(nèi)部有4K字節(jié)的Flash PEROM，這個(gè)Flash存儲(chǔ)陣列出廠時(shí)已處于擦除狀態(tài)（即所有存儲(chǔ)單元的內(nèi)容均為FFH），用戶隨時(shí)可對(duì)其進(jìn)行編程。編程接口可接收高電壓（+12V）或低電壓（VCC）的允許編程信號(hào)。低電壓編程模式適合于用戶在線編程系統(tǒng)，而高電壓編程模式可與通用EPROM編程器兼容。</p><p>　　AT89C51的程序存儲(chǔ)器陣

24、列是采用字節(jié)寫入方式編程的，每次寫入一個(gè)字節(jié)，要對(duì)整個(gè)芯片內(nèi)的PEROM程序存儲(chǔ)器寫入一個(gè)非空字節(jié)，必須使用片擦除的方式將整個(gè)存儲(chǔ)器的內(nèi)容清除。</p><p><b>　　編程方法：</b></p><p>　　編程前，須根據(jù)表設(shè)置好地址、數(shù)據(jù)及控制信號(hào)。AT89C51編程方法如下：</p><p>　　1、在地址線上加上要編程單元的地址信號(hào)

25、。</p><p>　　2、在數(shù)據(jù)線上加上要寫入的數(shù)據(jù)字節(jié)。</p><p>　　3、激活相應(yīng)的控制信號(hào)。</p><p>　　4、在高電壓編程方式時(shí)，將EA/VPP端加上+12V編程電壓。</p><p>　　5、每對(duì)Flash存儲(chǔ)陣列寫入一個(gè)字節(jié)或每寫入一個(gè)程序加密位，加上一個(gè)ALE/編程脈沖。改變編程單元的地址和寫入的數(shù)據(jù)，重復(fù)1—5步

26、驟，直到全部文件編程結(jié)束。每個(gè)字節(jié)寫入周期是自身定時(shí)的，通常約為1.5ms。</p><p><b>　　數(shù)據(jù)查詢：</b></p><p>　　AT89C51單片機(jī)用數(shù)據(jù)查詢方式來檢測(cè)一個(gè)寫周期是否結(jié)束，在一個(gè)寫周期中，如需讀取最后寫入的那個(gè)字節(jié)，則讀出的數(shù)據(jù)最高位是原來寫入字節(jié)最高位的反碼。寫周期完成后，有效的數(shù)據(jù)就會(huì)出現(xiàn)在所有輸出端上，此時(shí)，可進(jìn)入下一個(gè)字節(jié)的寫

27、周期，寫周期開始后，可在任意時(shí)刻進(jìn)行數(shù)據(jù)查詢。</p><p><b>　　程序校驗(yàn)：</b></p><p>　　如果加密位LB1、LB2沒有進(jìn)行編程，則代碼數(shù)據(jù)可通過地址和數(shù)據(jù)線讀回原編寫的數(shù)據(jù)。加密位不可直接校驗(yàn)，加密位的校驗(yàn)可通過對(duì)存儲(chǔ)器的校驗(yàn)和寫入狀態(tài)來驗(yàn)證。</p><p><b>　　芯片擦除：</b><

28、;/p><p>　　利用控制信號(hào)的正確組合并保持ALE/引腳10ms的低電平脈沖寬度即可將PEROM陣列（4K字節(jié)）和三個(gè)加密位整片擦除，代碼陳列在片擦除操作中將任何非空單元寫入“1”，這步驟需再編程之前進(jìn)行。</p><p><b>　　讀片內(nèi)簽名字節(jié)：</b></p><p>　　讀簽名字節(jié)的過程和單元030H、031H及032H的正常校驗(yàn)相仿

29、，只需將P3.6和P3.7保持低電平，返回值意義如下：</p><p>　　(030H)=1EH聲明產(chǎn)品由ATMEL公司制造</p><p>　　(031H)=51H聲明為AT89C51單片機(jī)</p><p>　　(032H)=FFH聲明為12V編程電壓</p><p>　　(032H)=05H聲明為5V編程電壓</p><

30、;p><b>　　編程接口：</b></p><p>　　采用控制信號(hào)的正確組合可對(duì)Flash閃速存儲(chǔ)陣列中的每一代碼字節(jié)進(jìn)行寫入和存儲(chǔ)器的整片擦除，寫操作周期是自身定時(shí)的，初始化后它將自動(dòng)定時(shí)到操作完成。</p><p>　　2.DS18B20 傳感器的介紹　　在傳統(tǒng)的模擬信號(hào)遠(yuǎn)距離溫度測(cè)量系統(tǒng)中，需要很好的解決引線誤差補(bǔ)償問題、多點(diǎn)測(cè)量切換誤差問題和放大電

31、路零點(diǎn)漂移誤差問題等技術(shù)問題，才能夠達(dá)到較高的測(cè)量精度。另外一般監(jiān)控現(xiàn)場(chǎng)的電磁環(huán)境都非常惡劣，各種干擾信號(hào)較強(qiáng)，模擬溫度信號(hào)容易受到干擾而產(chǎn)生測(cè)量誤差，影響測(cè)量精度[5]。因此，在溫度測(cè)量系統(tǒng)中，采用抗干擾能力強(qiáng)的新型數(shù)字溫度傳感器是解決這些問題的最有效方案， 與其它溫度傳感器相比DSl820 具有以下特點(diǎn)：　　(1)獨(dú)特的單線接口方式。DSl820 在與微處理器連接時(shí)僅需要一條接口線即可實(shí)現(xiàn)微處理器與DSl820 的雙向通訊。(2)

32、多點(diǎn)功能簡(jiǎn)化了分布式溫度檢測(cè)的應(yīng)用。(3)DSl820 在使用中無需任何外圍元件。(4)可用數(shù)據(jù)線供電，電壓范圍從3.0V 到5.5V。(5)可測(cè)量的溫度范圍從-55℃到+125℃，增量值0. 5℃；華氏溫度范圍從-67 到+257，增量值0．9。(6)支持多點(diǎn)組網(wǎng)功能。多個(gè)DS1820 可以并接在同一條總線上,實(shí)現(xiàn)多點(diǎn)測(cè)溫。(7)9 位的溫度分辨率。測(cè)量結(jié)果以9 位數(shù)字量方式串行傳送。(8)用戶可設(shè)定溫度報(bào)警門限值。(</p&g

33、t;<p>　　本文摘譯自：atmel ---AT89C51中文資料DATSHEET 規(guī)格書</p><p>　　DS18B20的英文數(shù)據(jù)手冊(cè) </p><p>　　DS18B20 Programmable Resolution 1-Wire </p><p>　　Digital Thermometer</p><

34、p>　　Based on SCM multi-functional temperature testing system design</p><p><b>　　1、preface</b></p><p>　　With the development of society and the technological progress, people pay m

35、ore and more attention to the importance of temperature detection and display. Temperature detection and status display technology and equipment has been widely applied in industries, products on the market emerge in end

36、lessly. Temperature testing and also gradually adopt the automatic control technology to realize the monitor. This topic is a temperature testing and status of the monitoring system.</p><p>　　2、System soluti

37、ons</p><p>　　This system USES the monolithic integrated circuit AT89C51 as this system. The whole system, the hardware circuit including power supply circuit, sensor, the temperature display circuit circuit,

38、 upper alarm circuit . The alarming circuit can be measured in upper temperature range, screaming voice alarm. The basic principle for the temperature control DSl8B20: when the temperature signal acquisition to after tem

39、perature signal sent to handle, AT89C51 temperature to LCD screen, SCM according to in</p><p>　　3、The system hardware design</p><p>　?。?）AT89C51 SCM are introduced</p><p>　　The AT89

40、C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM) and 128 bytes of data random-access memory(RAM). The device is manufactured using AT

41、MEL Co.’s high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set and pin-out. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conve

42、ntional nonvolatile memory programmer. By combining </p><p><b>　　Features:</b></p><p>　　·Compatible with instruction set of MCS-51 products</p><p>　　·4K bytes

43、of in-system reprogrammable Flash memory</p><p>　　·Endurance: 1000 write/erase cycles</p><p>　　·Fully static operation: 0 Hz to 24 MHz</p><p>　　·Three-level program m

44、emory lock</p><p>　　·128×8-bit internal RAM</p><p>　　·32 programmable I/O lines</p><p>　　·Two 16-bit Timer/Counters</p><p>　　·Six interrupt sou

45、rce</p><p>　　·Programmable serial channel</p><p>　　·Low-power idle and Power-down modes</p><p>　　Function Characteristic Description:</p><p>　　The AT89C51 pro

46、vides the following standard features: 4K bytes of Flash memory, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator a

47、nd clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RA

48、M, timer/counters, serial port and interrupt </p><p>　　Pin Description:</p><p>　　·VCC: Supply voltage</p><p>　　·GND: Ground</p><p>　　·Port 0: Port 0 is a

49、n 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs.</p><p>　　Port 0 may also

50、be configured to be the multiplexed low order address/bus during accesses to external program and data memory. In this mode P0 has internal pull ups. </p><p>　　Port 0 also receives the code bytes during Flas

51、h programming, and outputs the code bytes during program verification. External pull ups are required during program verification.</p><p>　　·Port 1: Port 1 is an 8-bit bidirectional I/O port with intern

52、al pull ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 1 pins that are external

53、ly being pulled low will source current (IIL) because of the internal pull ups. </p><p>　　Port 1 also receives the low-order address bytes during Flash programming and verification.</p><p>　　

54、83;Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pull ups an

55、d can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull ups.</p><p>　　Port 2 emits the high-order address byte during fetch

56、es from external program memory and during accesses to external data memory which uses 16-bit addresses (MOVX @ DPTR). In this application, it uses strong internal pull ups when emitting 1s. During accesses to external d

57、ata memory which uses 8-bit addresses (MOVX @ RI). Port 2 emits the contents of the P2 Special Function Register.</p><p>　　Port 2 also receives the high-order address bits and some control signals during Fla

58、sh programming and verification.</p><p>　　·Port 3: Port 3 is an 8-bit bi-directional I/O port with internal pull ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Po

59、rt 3 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull ups.</p><p>　　Port

60、 3 also receives some control signals for Flash programming and verification.</p><p>　　·RST: Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.<

61、/p><p>　　·ALE/: Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input () during Flash programming. In norma

62、l operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Me

63、mory.</p><p>　　If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high

64、. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.</p><p>　　·：Program Store Enable is the read strobe to external program memory. When the AT89C51 is execu

65、ting code from external program memory, is activated twice each machine cycle, except that two activations are skipped during each access to external data memory.</p><p>　　·EA/VPP：External Access Enab

66、le. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latc

67、hed on reset. EA should be strapped to VCC for internal program executions. </p><p>　　This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-v

68、olt VPP.</p><p>　　·XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit.</p><p>　　·XTAL2：Output from the inverting oscillator amplifier.&

69、lt;/p><p>　　·Ready/: The progress of byte programming can also be monitored by the RDY/output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again w

70、hen programming is done to indicate READY.</p><p>　　Oscillator Characteristics：</p><p>　　XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured

71、 for use as an on-chip oscillator. Either a quartz crystal or ceramic resonator may be used. </p><p>　　To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is drive

72、n.</p><p>　　There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide by two flip trigger, but minimum and maximum volta

73、ge high and low time specifications must be observed.</p><p>　　Idle Mode：</p><p>　　In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked

74、 by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.</p><p>

75、;　　It should be noted that when idle is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. O

76、n-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruc

77、tion following the one that invokes Idle should not be one that</p><p>　　Power-down Mode:</p><p>　　In the power-down mode, the oscillator is stopped, and the instruction that invokes power-down

78、is the last instruction executed. The on-chip RAM and special function registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the special

79、 function registers but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to al</p><p>　　Program Memo

80、ry Lock Bits:</p><p>　　When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value,

81、and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.</p><p>　　Pro

82、gramming the Flash:</p><p>　　The AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed. The programming interface accepts ei

83、ther a high-voltage (12-volt) or a low-voltage (VCC) program enable signal. The low-voltage programming mode provides a convenient way to program the AT89C51 inside the user’s system, while the high-voltage programming m

84、ode is compatible with conventional third party Flash or EPROM programmers.The AT89C51 is shipped with</p><p>　　The AT89C51 code memory array is programmed byte-by-byte in either programming mode. To program

85、 any nonblank byte in the on-chip Flash memory, the entire memory must be erased using the chip erase mode. </p><p>　　Programming Algorithm: </p><p>　　Before programming the AT89C51, the address

86、, data and control signals should be set up according to the Flash programming mode table .To program the AT89C51, take the following steps:</p><p>　　1. Input the desired memory location on the address lines

87、.</p><p>　　2. Input the appropriate data byte on the data lines.</p><p>　　3. Activate the correct combination of control signals.</p><p>　　4. Raise EA/VPP to 12V for the high-voltag

88、e programming mode.</p><p>　　5. Pulse ALE/once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5ms. Repeat steps 1 through 5, chan

89、ging the address and data for the entire array or until the end of the object file is reached.</p><p>　　Data Polling: </p><p>　　The AT89C51 features Data Polling to indicate the end of a write c

90、ycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next

91、 cycle may begin. Data polling may begin any time after a write cycle has been initiated.</p><p>　　Program Verify: </p><p>　　If lock bits LB1 and LB2 have not been programmed, the programmed cod

92、e data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.</p><p

93、>　　Chip Erase: </p><p>　　The entire Flash array is erased electrically by using the proper combination of control signals and by holding ALE/ low for 10 ms. The code array is written with all “1”s. The ch

94、ip erase operation must be executed before the code memory can be re-programmed.</p><p>　　Reading the Signature Bytes:</p><p>　　The signature bytes are read by the same procedure as a normal ver

95、ification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows:</p><p>　　(030H) = 1EH indicates manufactured by ATMEL</p><

96、p>　　(031H) = 51H indicates AT89C51 single-chip</p><p>　　(032H) = FFH indicates 12V programming</p><p>　　(032H) = 05H indicates 5V programming</p><p>　　Programming Interface:</

97、p><p>　　Every code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is self timed and once initiated,

98、will automatically time itself to completion.</p><p>　?。?）The sensor DS18B20</p><p>　　In the traditional analog signal distance temperature measuring system, need good solve lead error compensat

99、ion, multi-point measurement error and amplifying circuit switching technologies such as zero drift error problem, can achieve high measuring accuracy. Another general monitoring site of the electromagnetic environment i

100、s very bad, all kinds of jamming signal is stronger, the simulated temperature signal interference and vulnerable to produce measurement error and measuring precision [5]. </p><p>　　(1) the unique singleline

101、 interface way. DSl820 in connection with the microprocessor only need one interface to implement line DSl820 microprocessors and two-way communication. (2) more function simplifies distributed temperature detection appl

102、ication. (3) DSl820 in use without any peripheral devices. (4) power, voltage range data available from 3.0 V to 5.5 V. (5) can measure temperature range from - 55 degrees c + + to 125, incremental value 0. 5 ° c, F

103、ahrenheit temperature range from - 67 to</p><p>　?、?DSl8B20 principle of work</p><p>　　The internal structure of DS18B20 DSl8B20 temperature measurement principle diagram shown in figure 3.2. Lo

104、w temperature coefficient graph oscillation frequency vibration product temperature is used to produce with fixed frequency, pulse signal to counter l. High temperature coefficient crystals temperature-dependent its osci