外文翻譯--信息時(shí)代的機(jī)械工程學(xué)

1、<p>　　6500字?jǐn)?shù) </p><p><b>　　外文翻譯</b></p><p>　　信息時(shí)代的機(jī)械工程學(xué)</p><p>　　早在20世紀(jì)80年代，工程師認(rèn)為需要進(jìn)行大量實(shí)驗(yàn)因?yàn)榭s短的產(chǎn)品開(kāi)發(fā)循環(huán)促使工程師使用有效的技術(shù)。開(kāi)發(fā)一種用于新產(chǎn)品中的革命性技術(shù)是冒險(xiǎn)且易于失敗的，采取短的進(jìn)程對(duì)產(chǎn)品開(kāi)發(fā)來(lái)講是安全且更

2、易成功的途徑。</p><p>　　短的產(chǎn)品開(kāi)發(fā)循環(huán)在工程領(lǐng)域也是有利的，這個(gè)領(lǐng)域里，資本和勞動(dòng)力都是整體的。可以設(shè)計(jì)并制造不同產(chǎn)品的人在世界的任何地方都能夠找到，但有新思想的人就很難找到了。地理上的距離已經(jīng)不再是那些想在6個(gè)月內(nèi)將發(fā)明付諸于實(shí)踐的人的障礙了，如果你已經(jīng)獲得短的開(kāi)發(fā)循環(huán)，只要你保持領(lǐng)先形勢(shì)就不會(huì)是災(zāi)難性的，但如果你已經(jīng)處于六年的開(kāi)發(fā)的過(guò)程并且競(jìng)爭(zhēng)者已經(jīng)趕上你，那么這個(gè)項(xiàng)目就處于更嚴(yán)峻的麻煩中。&l

3、t;/p><p>　　工程師們?cè)诮鉀Q任何問(wèn)題時(shí)都需要進(jìn)行新的設(shè)計(jì)這種觀念很快就過(guò)事了。在現(xiàn)代設(shè)計(jì)中的第一步是瀏覽英特網(wǎng)或者其他信息系統(tǒng)，看其他人是否設(shè)計(jì)了一種類似于你所需要的產(chǎn)品，諸如傳動(dòng)裝置或者換熱器等。通過(guò)這些信息系統(tǒng)，你可能發(fā)現(xiàn)有些人已經(jīng)有了制造圖紙，數(shù)控紙帶和制造你的產(chǎn)品所需要的其他所有東西。這樣，工程師們就可以把他們的職業(yè)技能集中在尚未解決的問(wèn)題上。</p><p>　　在解決這類問(wèn)

4、題時(shí)，利用工作站和進(jìn)入信息高速公路可以大大增強(qiáng)工程小組的能力和效率。這些信息時(shí)代的工具可使工程小組利用大規(guī)模的數(shù)據(jù)庫(kù)。數(shù)據(jù)庫(kù)中有材料性能、標(biāo)準(zhǔn)、技術(shù)和成功的設(shè)計(jì)方案等信息。這些經(jīng)過(guò)驗(yàn)證的設(shè)計(jì)可以通過(guò)下載直接應(yīng)用，或者通過(guò)對(duì)其進(jìn)行快速、簡(jiǎn)單的改進(jìn)來(lái)滿足特定的要求。將產(chǎn)品的技術(shù)要求通過(guò)網(wǎng)絡(luò)送出去的遠(yuǎn)程制造也是可行的。你可以建立一個(gè)沒(méi)有任何加工設(shè)備的虛擬公司，可以指示制造商，在產(chǎn)品加工往常后，將其直接送給你的客戶。定期訪問(wèn)你的客戶可以保證你設(shè)

5、計(jì)的產(chǎn)品按照設(shè)計(jì)要求進(jìn)行工作。盡管這些研制開(kāi)發(fā)方式不可能對(duì)每個(gè)公司都完全適用，但是這種可能性是存在的。</p><p>　　傳統(tǒng)設(shè)計(jì)通常用于小公司，大公司嘲諷這種做法，他們討厭處理服務(wù)市場(chǎng)成為少量主顧解決問(wèn)題的思想：“這是我的產(chǎn)品”。一家大公司的人會(huì)說(shuō)：“這是我能做的最好的產(chǎn)品了，你一定會(huì)喜歡它的，但如果你不喜歡的話。這條街下邊有一家更小的公司可以解決你的問(wèn)題?！?lt;/p><p>　　當(dāng)今

6、，幾乎每家市場(chǎng)都是服務(wù)市場(chǎng)，因?yàn)轭櫩褪怯羞x擇性的。如果你忽視了修改產(chǎn)品來(lái)滿足顧客要求的潛在可能性。你將失去市場(chǎng)的主要部分甚至全部，盡管這些服務(wù)市場(chǎng)是臨時(shí)的，但你的公司需要以一定的時(shí)間盡快答復(fù)他們所需要的。</p><p>　　瞄準(zhǔn)機(jī)會(huì)的市場(chǎng)和根據(jù)客戶要求盡心干涉機(jī)這種現(xiàn)象的出現(xiàn)，改變了工程師們進(jìn)行研究工作的方式。今天，研究工作通常是針對(duì)解決特定問(wèn)題進(jìn)行的。許多由政府資助或者由大公司出資開(kāi)發(fā)的技術(shù)可以在非常低成本下

7、被自由使用，盡管這種情況可能是暫時(shí)的。在對(duì)這些技術(shù)進(jìn)行適當(dāng)改進(jìn)后，它們通常能夠被直接用于產(chǎn)品開(kāi)發(fā)，這使得許多公司可以節(jié)省昂貴的研究經(jīng)費(fèi)。在主要的技術(shù)障礙被克服后，研究工作應(yīng)該主要致力于產(chǎn)品的商品化方面，而不是開(kāi)發(fā)新的，有趣的，不確定的替換產(chǎn)品。</p><p>　　當(dāng)涉及遠(yuǎn)景的時(shí)候，采用上述觀點(diǎn)看問(wèn)題，工程研究應(yīng)該致力于消除將已知技術(shù)快速商品化的障礙。工作的重點(diǎn)是產(chǎn)品的自量和可靠性，這些在當(dāng)今的顧客的頭腦中是最重

8、要的。很明顯，一個(gè)自量差的聲譽(yù)是一個(gè)不好的企業(yè)的同義詞。企業(yè)應(yīng)該盡最大努力來(lái)保證顧客得到合格的產(chǎn)品，這個(gè)努力包括在生產(chǎn)線的終端對(duì)產(chǎn)品進(jìn)行嚴(yán)格的檢驗(yàn)和自動(dòng)更換有缺陷的產(chǎn)品。</p><p>　　研究必須考慮到可靠性等因素的成本利益當(dāng)可靠性提高時(shí)，制造成本和次同的最終成本內(nèi)將會(huì)降低。如果在生產(chǎn)線的終端生產(chǎn)30%的廢品，這不僅會(huì)浪費(fèi)金錢，也會(huì)給你的競(jìng)爭(zhēng)對(duì)手創(chuàng)造一個(gè)利用你的想法制造產(chǎn)品，而且也為競(jìng)爭(zhēng)者提供了采用你的設(shè)計(jì)賣

9、給顧客的機(jī)會(huì)。</p><p>　　提高可靠性并且降低成本這個(gè)過(guò)程的關(guān)鍵是深入、廣泛地利用設(shè)計(jì)軟件。設(shè)計(jì)軟件可以使工程師們加快每個(gè)階段的設(shè)計(jì)工作。然而，僅僅縮短每個(gè)階段的設(shè)計(jì)時(shí)間，可能不會(huì)顯著的縮短整個(gè)設(shè)計(jì)過(guò)程的時(shí)間。因而，必須致力于采用并行工程軟件，這樣可以使所設(shè)計(jì)組的成員都能使用共同的數(shù)據(jù)庫(kù)。</p><p>　　隨著我們更加完全的進(jìn)入信息時(shí)代，成功需要工程師掌握一些有關(guān)發(fā)明和技術(shù)管理

10、的獨(dú)特知識(shí)和經(jīng)驗(yàn)。</p><p>　　成功的工程師們不但應(yīng)該具有寬廣的知識(shí)和技能，而且還應(yīng)該是某些關(guān)鍵技術(shù)或?qū)W科的專家，他們還應(yīng)該在社會(huì)因素對(duì)市場(chǎng)的影響方面有敏銳的洞察能力。將來(lái)，花在解決日常工程問(wèn)題上的花費(fèi)將會(huì)減少，工程師們將會(huì)在一些更富有挑戰(zhàn)，更亟待解決的問(wèn)題上協(xié)同工作，大大縮短解決這些問(wèn)題所需要的時(shí)間。我們已經(jīng)開(kāi)始了工程實(shí)踐的新階段。計(jì)算機(jī)和網(wǎng)絡(luò)使工程師們具有越來(lái)越強(qiáng)的解決問(wèn)題的能力，這也給他們的工作帶來(lái)

11、很大的希望和喜悅。為了確保成功，我們使用的工具的性能和對(duì)更好的產(chǎn)品與系統(tǒng)的不斷要求，應(yīng)該與標(biāo)志著在工程方面所有巨大努力的創(chuàng)新工作所帶來(lái)的喜悅相適應(yīng)。機(jī)械工程是一個(gè)偉大的行業(yè)，在我們盡可能多地利用了信息時(shí)代所提供的機(jī)遇后，它將變得更加美好。</p><p>　　微處理器系統(tǒng)可以在許多復(fù)雜程度不同的層次上進(jìn)行描述。最簡(jiǎn)單復(fù)雜形式是描述不同功能上調(diào)解信息的相互作用和流動(dòng)的簡(jiǎn)單的素描簡(jiǎn)圖并且會(huì)用于測(cè)試微處理系統(tǒng)的操作。&

12、lt;/p><p>　　所有微機(jī)系統(tǒng)包含一個(gè)中央處理單元（CPU）、程序和數(shù)據(jù)存儲(chǔ)器以及輸入、輸出（I/O）設(shè)備。</p><p>　　存儲(chǔ)部分包含了用作程序存儲(chǔ)器的掉電不易失信息的只讀存儲(chǔ)器（ROM）和用作讀/寫的掉電易失的隨機(jī)訪問(wèn)數(shù)據(jù)存儲(chǔ)器（RAM），每種存儲(chǔ)器都有許多不同類型的元件，如可寫的ROM以及靜態(tài)或動(dòng)態(tài)的RAM，應(yīng)用時(shí)根據(jù)價(jià)格、功能來(lái)選擇應(yīng)用的。</p><p

13、>　　微處理器的模擬輸入路線是由模擬數(shù)字轉(zhuǎn)化器提供的，并且可用于連接，如模擬感應(yīng)元件的裝置，模擬輸出路線是又?jǐn)?shù)字模擬轉(zhuǎn)化器提供的并且可用于控制，像電動(dòng)機(jī)一樣的輸出換能器，平行I/O裝置提供了大量單獨(dú)的路線。在輸出模型中這些可以編成程序來(lái)提供邏輯符1或0采用激活電平裝置，例如燈在輸入模型中允許微處理器度曲轉(zhuǎn)變狀況和其他電平裝置，串行的I/O裝置用來(lái)提供。同其他微處理系統(tǒng)或用于不同操作模型的成型系統(tǒng)中的操作控制臺(tái)的對(duì)話。微處理系統(tǒng)的接

14、口信號(hào)的等級(jí)和能量規(guī)格通常和與之接口的裝置的信號(hào)規(guī)格不相匹配，例如D/A轉(zhuǎn)換器所輸出電壓一般在0-5V范圍內(nèi)，反能提高小伏安電流，而電機(jī)需要在范圍（-12V-12V）控制電壓最大電流安培。因此，附加的模擬接口電路系統(tǒng)通常有必要發(fā)揮功能，例如信號(hào)平轉(zhuǎn)化擴(kuò)大和過(guò)濾。</p><p>　　所有這些裝置都通過(guò)系統(tǒng)總線與CPU連接，用一種系統(tǒng)母線的方法。系統(tǒng)母線本身由地址母線，數(shù)據(jù)母線和控制母線組成的。實(shí)際上，母線是兩個(gè)或

15、多個(gè)裝置間平行線的簡(jiǎn)單連接。每條母線中包括的線條數(shù)是根據(jù)用于系統(tǒng)中的微處理器類型和母線功能決定的。我們假設(shè)地址母線有十六條線，數(shù)據(jù)母線有八條線，控制母線包括CPU提供的控制功能而定的一定數(shù)量的線路。</p><p>　　地址和數(shù)據(jù)是運(yùn)行計(jì)算機(jī)儲(chǔ)存的程序、形成所有微處理器和計(jì)算機(jī)特征的基礎(chǔ)。存儲(chǔ)器由許多能由CPU通過(guò)數(shù)據(jù)總線寫如數(shù)據(jù)的存儲(chǔ)單元構(gòu)成。每個(gè)存儲(chǔ)單元具體位置由CPU用地址來(lái)唯一標(biāo)識(shí)。為了從存儲(chǔ)器或I/O設(shè)

16、備中寫或讀信息，CPU控制著地址和控制總線， CPU希望將二進(jìn)制信息寫入地址的存儲(chǔ)單元，CPU首先將該地址送到地址總線上，然后作為數(shù)據(jù)送到數(shù)據(jù)總線上，控制總線中的控制線激活，啟動(dòng)數(shù)據(jù)寫入適當(dāng)?shù)拇鎯?chǔ)單元。相類似的情況用于CPU只讀存儲(chǔ)單元的地址送到地址的過(guò)程，這時(shí)數(shù)據(jù)流不是從存儲(chǔ)器到CPU，那么在CPU將要求的存儲(chǔ)單元的地址送到地址總線上后，CPU通過(guò)啟動(dòng)控制總線相關(guān)的控制線，指示存儲(chǔ)器要讀數(shù)據(jù)，存儲(chǔ)器則做出反應(yīng)，將該存儲(chǔ)單元的內(nèi)容當(dāng)作數(shù)

17、據(jù)，送上數(shù)據(jù)總線，然后CPU讀取到該數(shù)據(jù)。</p><p>　　在系統(tǒng)總線中，地址總線對(duì)CPU來(lái)說(shuō)是輸出總線，但對(duì)其他設(shè)備是輸入總線，控制總線包含許多線或者是CPU輸出控制線，或者是輸入控制線。數(shù)據(jù)總線既當(dāng)作輸入總線，又作輸出總線，這要看CPU是讀還是寫數(shù)據(jù)，系統(tǒng)中所有元件都通過(guò)數(shù)據(jù)總線連接在一起，這意味著，最低限度上存儲(chǔ)器和I/O設(shè)備的輸出是連在一起的。例如感實(shí)際情況就是這樣，則將引起所有連接的元件中幾個(gè)或全部

18、元件破壞，因?yàn)橐恍┰⒃噲D驅(qū)動(dòng)總線到邏輯1狀態(tài)，而其他一些則試圖驅(qū)動(dòng)其為邏輯0狀態(tài)。為了避免這個(gè)問(wèn)題，連接到每個(gè)元件的數(shù)據(jù)總線有第三種狀態(tài)即高阻態(tài)，在這種狀態(tài)下元件對(duì)總線不再有負(fù)載的影響，這就使連接到數(shù)據(jù)總線上的其他元件在需要時(shí)能將數(shù)據(jù)送上數(shù)據(jù)總線，這也就意味著在某一時(shí)刻僅有一個(gè)元件與數(shù)據(jù)總線相通。一個(gè)元件處于數(shù)據(jù)總線的邏輯1、邏輯0或處于有關(guān)于數(shù)據(jù)母線的高電阻條件下的能力被稱為tristate條件。這是共享相同的數(shù)據(jù)總線的設(shè)備重要的

19、特性。</p><p>　　數(shù)據(jù)總線為8根因此能得到的單個(gè)數(shù)據(jù)被8位二進(jìn)制數(shù)所限制，八位指一個(gè)字節(jié)，能代表從0到255的十進(jìn)制；同樣地，地址總線包含16根線，能代表的地址范圍從0到216-1或65535，這個(gè)數(shù)字常常被縮寫成與二進(jìn)制等價(jià)的十進(jìn)制數(shù)，表示成16K，1K在二進(jìn)制系統(tǒng)中等于1024，對(duì)于CPU而言，系統(tǒng)就像一連串的64K的連續(xù)的存儲(chǔ)單元，每個(gè)單元可存放8位二進(jìn)制數(shù)。</p><p&g

20、t;　　CPU包含許多寄存器，它們用語(yǔ)處理數(shù)據(jù)和地址，在所選擇的例子中，這些數(shù)據(jù)寄存器為8位的寄存器，所有的數(shù)據(jù)操作都上都是8位，因此CPU就指8位CPU，但是支持地址操作的寄存器需16位，因?yàn)榈刂房偩€是16位的。地址總線的寬度與數(shù)據(jù)總線的寬度是獨(dú)立的，因此16位或32位CPU典型的有16 位，24位或32位地址總線。</p><p>　　通常對(duì)微處理操作時(shí)用十六進(jìn)制（基于16）值代表二進(jìn)制數(shù)，因?yàn)橐粋€(gè)十六進(jìn)制數(shù)

21、與四位連續(xù)的二進(jìn)制數(shù)相對(duì)應(yīng)。十六進(jìn)制數(shù)比相等的二進(jìn)制數(shù)量易讀學(xué)，并且只需簡(jiǎn)單的換算就能將十六進(jìn)制數(shù)與二進(jìn)制數(shù)互譯，十六進(jìn)制數(shù)在文本中是用前綴OX標(biāo)識(shí)，這是在C變成語(yǔ)言中所采用的。</p><p>　　硬件設(shè)計(jì)者沒(méi)有必要使用整個(gè)CPU的地址空間，所要求的存儲(chǔ)器可以在CPU地址空間的任何地方執(zhí)行，另外I/O裝置可以成型，并且可以提供地址，通過(guò)這個(gè)地址CPU可以讀取和記錄進(jìn)出系統(tǒng)的數(shù)據(jù)。這些存儲(chǔ)器是以普通存儲(chǔ)點(diǎn)出現(xiàn)于C

22、PU。并占據(jù)地址空間的位置。地址空間中存儲(chǔ)排雷和I/O地址通過(guò)系統(tǒng)存儲(chǔ)圖描述。</p><p>　　存儲(chǔ)圖是為了滿足設(shè)計(jì)應(yīng)用的要求，并且被硬件設(shè)計(jì)者用來(lái)分割空間以便使系統(tǒng)中存儲(chǔ)設(shè)備的地址范圍與存儲(chǔ)映象圖詳細(xì)列出的地址相一致，所以系統(tǒng)中存儲(chǔ)裝置的地址域相當(dāng)于存儲(chǔ)圖中的地址域。其可以作為輸入通過(guò)地址母線獲得并且為每個(gè)貢獻(xiàn)于系統(tǒng)存儲(chǔ)圖的芯片分割出獨(dú)立的良好的芯片信號(hào)。</p><p><b

23、>　　英文原文</b></p><p>　　Mechanical Engineering in the Information Age</p><p>　　In the early 1980s, engineers thought that massive research would be needed because shortened product develop

24、ment cycles encourage engineers to use available technology. Developing a revolutionary technology for use in a new product is risky and prone to failure. Taking short steps is a safer and usually more successful approac

25、h to product development. </p><p>　　Shorter product development cycles are also beneficial in an engineering world in which both capital and labor are global. People who can design and manufacture various pr

26、oducts can be found anywhere in the world, but containing a new idea is hard. Geographic distance is no longer a barrier to others finding out about your development six months into the process. If you’ve got a short dev

27、elopment cycle, the situation is not catastrophic as long as you maintain your lead. But if you’ve in the mid</p><p>　　The idea that engineers need to create a new design to solve every problem is quickly be

28、coming obsolete. The first step in the modern design process is to browse the Internet or other information systems to see if someone else has already designed a transmission, or a heat exchanger that is close to what yo

29、u need. Through these information systems, you may discover that someone already has manufacturing drawings, numerical control tapes, and everything else required to manufacture your product. </p><p>　　In ta

30、ckling such problems, the availability of workstations and access to the information highway dramatically enhance the capability of the engineering team and its productivity. These information age tools can give the team

31、 access to massive databases of material properties, standards, technologies, and successful designs. Such pretested designs can be downloaded for direct use or quickly modified to meet specific needs. Remote manufacturi

32、ng, in which product instructions are sent out over a n</p><p>　　Custom design used to be left to small companies. Big companies sneered at it they hated the idea of dealing with niche markets or small-volum

33、e custom solutions. “Here is my product,” one of the big companies would say. “This is the best we can make it you ought to like it. If you don’t, there’s a smaller company down the street that will work on your problem.

34、”</p><p>　　Today, nearly every market is a niche market, because customers are selective. If you ignore the potential for tailoring your product to specific customers’ needs, you will lose the major part of

35、your market share perhaps all of it. Since these niche markets are transient, your company needs to be in a position to respond to them quickly.</p><p>　　The emergence of niche markets and design on demand h

36、as altered the way engineers conduct research.Today, research is commonly directed toward solving particular problems. Although this situation is probably temporary, much uncommitted technology, developed at government e

37、xpense or written off by major corporations, is available today at very low cost. Following modest modifications, such technology can often be used directly in product development, which allows many organizations to avoi

38、d the e</p><p>　　When viewed in this perspective, engineering research must focus primarily on removing the barriers to rapid commercialization of known technologies, Much of this effort must address quality

39、 and reliability concerns, which are foremost in the minds of today’s consumers. Clearly, a reputation for poor quality is synonymous with bad business. Everything possible including thorough inspection at the end of the

40、 manufacturing line and automatic replacement of defective products—must be done to assure</p><p>　　Research has to focus on the cost benefit of factors such as reliability. As reliability increases, manufac

41、turing costs and the final cost of the system will decrease. Having 30percent junk at the end of a production line not only costs a fortune but also creates an opportunity for a competitor to take your idea an sell it to

42、 your customers.</p><p>　　Central to the process of improving reliability and lowering costs is the intensive and widespread use of design software, which allows engineers to speed up every stage of the desi

43、gn process. Shortening each stage, however, may not sufficiently reduce the time required for the entire process. Therefore, attention must also be devoted to concurrent engineering software with shared databases that ca

44、n be accessed by all members of the design team.</p><p>　　As we move more fully into the Information Age, success will require that the engineer possess some unique knowledge of and experience in both the de

45、velopment and the management of technology. Success will require broad knowledge and skills as well as expertise in some key technologies and disciplines; it will also require a keen awareness of the social and economic

46、factors at work in the marketplace. Increasingly, in the future, routine problems will not justify heavy engineering expenditures, </p><p>　　A microprocessor system can be described at a number of different

47、levels of complexity. The least complex form is that of a simple block diagram describing the interconnection and flow of information between functional blocks and will be used to examine the operation of a microprocesso

48、r system.</p><p>　　All microprocessor systems contain a central processing uniy (CPU),program and data memory and input and output(I/O) devices. </p><p>　　The memory section contains both non-vo

49、latile read only memory (ROM) as program memory and volatile random access memory (RAM) as read/write data memory. For each type of memory there are a number of different types of devices, such as erasable ROMs and stati

50、c or dynamic RAMs, each of which is chosen for an application based on its cost and function.</p><p>　　An analogue input channel to the microprocessor system is provided by the analogue to digital (A/D) conv

51、erter and may be used to connect a device such as an analogue sensor. An analogue output channel is provided by the digital to analogue (D/A) converter and could be used to control an output transducer such as an electri

52、c motor. The parallel I/O device provides a number of individual lines. In output mode these can be programmed to provide logic levels 1 or 0 to activate binary (on/off) devic</p><p>　　The level and power s

53、pecifications of the interfacing signals of the microprocessor system are frequently incompatible with the signal specifications of the devices which are to be interfaced to it. For example, the output voltage of a D/A c

54、onverter may typically be in the range 0-5 volts and be capable of supplying only a few milliamperes of current, while the electric motor may require a control voltage range of plus and minus 12 volts at a maximum curren

55、t of 1 ampere. Consequently, additional</p><p>　　All these devices are interfaced to the CPU by means of a system bus which is itself made up form an address bus , a data bus and a control bus. Physically, a

56、 bus is simply a collection of parallel interconnections between two or more devices. The number of lines contained in each bus is dependent on the type of microprocessor used in the system and the function of the bus. w

57、e assume that the address bus has sixteen lines, the data bus has eight lines, and the control bus contains an arbitrary n</p><p>　　The concepts of address and data are fundamental to the operation of a stor

58、ed program computer and form a feature of all microprocessors and computes. The memory will consist of a number of memory locations capable of storing data written to them by the CPU over the data bus, each memory locati

59、on is uniquely identified to the CPU by a number called its address. The CPU controls the address and control bus lines in order to write or read information to or from the memory or I/O devices. If the CP</p><

60、;p>　　A similar procedure would be used if the CPU was then to read a memory address, except this time the flow of data would be from the memory to the CPU. After the CPU had placed the address of the required memory l

61、ocation on the address bus, it would indicate to the memory would respond by placing the contents of the memory location as data on to the data bus, and this would then be read by the CPU.</p><p>　　Within th

62、e system bus, the address bus is an output bus from the CPU and an input bus to the other devices. The control bus consists of a number of lines, each of which may be either a control output from the CPU or a control inp

63、ut to the CPU is reading or writing data. All devices in the system are connected together by the data bus and this means that, potentially at least, the outputs of all the memory and I/O devices are connected. If this w

64、ere in fact to happen it would cause the destructio</p><p>　　The data bus has eight lines, and hence the range of values which a single item of data can take is restricted to that which can be represented by

65、 8 binary digits or bits. Eight bits are referred to as a byte, and can represent a decimal number from 0 to 255. likewise the address bus, consisting of sixteen lines, can represent an address number in the range 0 to

66、216-1 or 65535. this number is usually abbreviated to the binary equivalent of the decimal number and expressed as 64k, where 1k is eq</p><p>　　The CPU will contain a number of registers which are used to ma

67、nipulate the data and its addresses. In the example chosen, these data registers will be 8 bit registers and all data bit CPU, However, registers which support address manipulations will be performed on 8 bit quantities.

68、 The CPU is therefore referred to as an 8 bit CPU. However, registers which support address manipulations need to be 16 bit registers because of the 16 bit address bus. The size of the address bus is independent of th<

69、;/p><p>　　It is normal when working with microprocessors to represent binary numbers as hexadecimal values, because a single hexadecimal digit corresponds to a group of fore consecutive binary digits. The hexad

70、ecimal number is easier to read and write than its binary equivalent, and it requires only simple mental calculation in order to translate from hexadecimal to binary and back again. Hexadecimal numbers and digits are ide

71、ntified in the text by prefixing them with 0x, which is the convention adopted i</p><p>　　It is not necessary for the hardware designer to make use of the entire address range of the CPU, and the physical me

72、mory required can be implemented anywhere within the address space of the CPU. In addition, the I/O devices will contain registers through which the I/O devices may be configured, and which provide addresses through whic

73、h the CPU can read and write data into and out of the system. These registers appear to the CPU as normal memory locations. And so occupy parts of the address spac</p><p>　　The memory map will be designed to

74、 meet the requirements of the application, and will be used by the hardware designer to partition the address space so that the address range of the memory devices in the system corresponds to the address range specified

75、 by the memory map. This is achieved by means of the address bus as its input and produces individual chip select signals for each chip select signals for each chip which contributes to the memory map of the system.</