語音控制器畢業(yè)設計外文翻譯

1、<p>　　SPCE061A 32K x 16 SOUND CONTROLLER</p><p>　　1. GENERAL DESCRIPTION</p><p>　　The SPCE061A, a 16-bit architecture product, carries the newest 16-bit microprocessor, μ’nSP? (pronounced

2、as micro-n-SP), developed by Sunplus Technology. This high processing speed assures the μ’nSP? is capable of handling complex digital signal processes easily and rapidly. Therefore, the SPCE061A is applicable to the area

3、s of digital sound process and voice recognition. The operating voltage of 3.0V through 3.6V and speed of 0.32MHz through 49.152MHz yield the SPCE061A to be easily used in va</p><p>　　BLOCK DIAGRAM</p>

4、<p>　　3. FEATURES</p><p>　　􀂄 16-bit μ’nSP? microprocessor</p><p>　　􀂄 CPU clock: 0.32MHz - 49.152MHz</p><p>　　􀂄 Operating voltage: 3.0V - 3.6V</p

5、><p>　　􀂄 Program Flash Operating voltage: 3.0V - 3.6V</p><p>　　􀂄 IO PortA & B operating voltage: 3.0V - 5.5V</p><p>　　􀂄 32K-word flash memory</p>

6、<p>　　􀂄 2K-word working SRAM</p><p>　　􀂄 Software-based audio processing</p><p>　　􀂄 Crystal Resonator</p><p>　　􀂄 Standby mode (Clock Stop mod

7、e) for power savings,</p><p>　　Max. 2.0μA @ VDD = 3.6V</p><p>　　􀂄 Two 16-bit timers/counters</p><p>　　􀂄 Two 10-bit DAC outputs</p><p>　　􀂄 32

8、general I/Os (bit programmable)</p><p>　　􀂄 14 INT sources with two priority levels</p><p>　　􀂄 Key wakeup function (IOA0 - 7)</p><p>　　􀂄 Approx. 190 sec sp

9、eech @ 2.0Kbit/per sec with SACM_S200</p><p>　　􀂄 PLL feature for system clock</p><p>　　􀂄 32768Hz Real Time Clock (RTC)</p><p>　　􀂄 Eight channels 10-bit AD

10、 converter</p><p>　　􀂄 ADC external top reference voltage</p><p>　　􀂄 2.0V voltage regulator output, 5mA of driving capability</p><p>　　􀂄 Serial interface I

11、/O (SIO)</p><p>　　􀂄 Built-in microphone amplifier and AGC function</p><p>　　􀂄 UART receiver and transmitter (full duplex)</p><p>　　􀂄 Low voltage reset and

12、 low voltage detection</p><p>　　􀂄 Watchdog enable (bonding option)</p><p>　　􀂄 ICE function for development and down load into flash memory</p><p>　　􀂄 Secu

13、rity function to protect code to be read and written.</p><p>　　4. APPLICATION FIELD</p><p>　　􀂄 Voice recognition products</p><p>　　􀂄 Intelligent interactive talkin

14、g toys</p><p>　　􀂄 Advanced educational toys</p><p>　　􀂄 Kids learning products</p><p>　　􀂄 Kids storybook</p><p>　　􀂄 General speech sy

15、nthesizer</p><p>　　􀂄 Long duration audio products</p><p>　　􀂄 Recording / playback products</p><p>　　SIGNAL DESCRIPTIONS</p><p>　　5. FUNCTIONAL DESCRIP

16、TIONS</p><p><b>　　5.1. CPU</b></p><p>　　The SPCE061A is equipped with a 16-bit μ’nSP?, the newest 16-bit microprocessor by Sunplus and pronounced as micro-n-SP. Eight registers are i

17、nvolved in μ’nSP?: R1 - R4 (General-purpose registers), PC (Program Counter), SP (Stack Pointer), Base Pointer (BP) and SR (Segment Register). The interrupts include three FIQs (Fast Interrupt Request) and eight IRQs (In

18、terrupt Request), plus one software-interrupt, BREAK.</p><p>　　Moreover, a high performance hardware multiplier with the capability of FIR filter is also built in to reduce the software multiplication loadin

19、g.</p><p>　　5.2. Memory</p><p>　　5.2.1. SRAM</p><p>　　The amount of SRAM is 2K-word (including Stack), ranged from $0000 through $07FF with access speed of two CPU clock cycles.<

20、/p><p>　　5.2.2. Flash memory</p><p>　　Flash memory ($008000 ~ $00FFFF) is a high-speed memory with access speed of two CPU clock cycles. FLASH erase and program functions must be used in IDE tools.

21、</p><p>　　5.3. PLL, Clock, Power Mode</p><p>　　5.3.1. PLL (Phase Lock Loop)</p><p>　　The purpose of PLL is to provide a base frequency (32768Hz) and to pump the frequency from 20.48

22、MHz to 49.152MHz for system clock (Fosc). The default PLL frequency is 24.576MHz.</p><p>　　5.3.1.1. System clock</p><p>　　Basically, the system clock is provided by PLL and programmed by the Por

23、t_SystemClock (W) to determine the frequency of clock for system. The default system clock Fosc = 24.576MHz and CPU clock is Fosc/8 if not specified. The initial CPU clock is Fosc/8 after system wakes up and to be adjust

24、ed to desired CPU clock by programming the Port_SystemClock (W). This avoids Flash ROM reading failure when system wakes up.</p><p>　　5.3.1.2. 32768Hz RTC</p><p>　　The Real Time Clock (RTC) is n

25、ormally used in watch, clock or other time related products. A 2Hz-RTC (1/2 second) function is loaded in SPCE061A. The RTC counts the timing as well as to wake CPU up whenever RTC occurs. Since the RTC is generated each

26、 0.5 seconds, time can be traced by the numbers of RTC occurrence. In addition, SPCE061A supports 32768Hz oscillator in normal mode and auto-power-saving mode. In normal mode, 32768Hz OSC always runs at the highest power

27、 consumption. In auto-power-sa</p><p>　　5.4. Standby Mode</p><p>　　The SPCE061A also offers a standby mode for low power application needs. To enter standby mode, the desired key wakeup port (IO

28、A [7:0]) must be configured to input first. And read the Port_IOA_Latch(R) to latch the IOA state before entering the standby mode. Also remember to enable the corresponding interrupt source(s) for wakeup. After that, st

29、op the CPU clock by writing the STOP CLOCK Register (b0~b2 of Port_SystemClock (W)) to enter standby mode. In such mode, SRAM and I/Os remain in the prev</p><p>　　5.5. Low Voltage Detection and Low Voltage R

30、eset </p><p>　　5.5.1. Low voltage detection (LVD) </p><p>　　There are two LVD levels to be selected: 2.9V, and 3.3V. These levels can be programmed via Port_LVD_Ctrl (W). As an example, suppose

31、LVD is given to 2.9V. When the voltage drops below 2.9V, the b15 of Port_LVD_Ctrl is read as HIGH. In such state, program can be designed to react to this condition. </p><p>　　5.5.2. Low voltage reset </p

32、><p>　　In addition to the LVD, the SPCE061A has another important function, Low Voltage Reset (LVR). With the LVR function, a reset signal is generated to reset system when the operating voltage drops below 2.3

33、V for 10 consecutive CPU clock cycles. Without LVR, the CPU becomes unstable and malfunctions when the operating voltage drops below 2.3V. The LVR will reset all functions to the initial operational (stable) states when

34、the voltage drops below 2.3V. A LVR timing diagram is given as follows: </p><p>　　5.6. Interrupt</p><p>　　The SPCE061A has 14 interrupt sources, grouped into two types, FIQ (Fast Interrupt Reque

35、st) and IRQ (Interrupt request). The priority of FIQ is higher than IRQ. FIQ is the high-priority interrupt while IRQ is the low-priority one. An IRQ can be interrupted by a FIQ, but not by another IRQ. A FIQ cannot be i

36、nterrupted by any other interrupt sources.</p><p><b>　　5.7. I/O</b></p><p>　　Two I/O ports are built in SPCE061A, PortA and PortB. The PortA is an ordinary I/O with programmable wake

37、up capability. In addition to the regular IO function, the PortB can also perform some special functions in certain pins. Suppose operating voltage is running at 3.6V (VDD) and VDDIO (power for I/O) operates from 3.6V (V

38、DD) to 5.5V. In such condition, the I/O pad is capable of operating from 0V through VDDIO. However IOB13 and IOB14 are recommended to operate <=3.6V during standby mode, other</p><p>　　Although data can b

39、e written into the same register through Port_Data and Port_Buffer, they can be read from different places, Buffer (R) and Data (R). The IOA [7:0] is the key wakeup port. To activate key wakeup function, latch data on PO

40、RT_IOA_Latch and enable the key wakeup function. Wakeup is triggered when the PortA state is different from at the time latched. In addition to an ordinary I/O port, PortB carries some special functions. A summary of Por

41、tB special functions is listed as follows</p><p>　　Refer to the above table, the configuration of IOB2, IOB3, IOB4, and IOB5 involves feedback function in which an OSC frequency can be obtained from EXT1 (EX

42、T2) by simply adding a RC circuit between IOB2 (IOB3) and IOB4 (IOB5).</p><p>　　5.8. Timer / Counter</p><p>　　The SPCE061A provides two 16-bit timers/counters, TimerA and TimerB. The TimerA is c

43、alled a universal counter. TimerB is a general-purpose counter. The clock source of TimerA comes from the combination of clock source A and clock source B. In TimerB, the clock source is given from source C. When timer o

44、verflows, an INT signal is sent to CPU to generate a time-out signal.</p><p>　　Initially, write a value of N into a timer and select a desired clock source, timer will start counting from N, N+1, N+2, ... th

45、rough FFFF. An INT (TimerA/TimerB) signal is generated at the next clock after reaching “FFFF” and the INT signal is transmitted to INT controller for further processing. At the same time, N will be reloaded into timer a

46、nd start all over again. The clock source A is a high frequency source and clock source B is a low frequency source. The combination of clock source A a</p><p>　　The following example is a 3/16-duration cycl

47、e. The APWMO waveform is made by selecting a pulse width through Port_TimerA_Ctrl (W) [9:6]. As a result, each 16 cycles will generate a pulse width defined in control port. These PWM signals can be applied for controlli

48、ng the speed of motor or other devices.</p><p>　　Generally speaking, the clock source A and C are fast clock sources and source B comes from RTC system (32768Hz). Therefore, clock source B can be utilized as

49、 a precise counter for time counting, e.g., the 2Hz clock can be used for real time counting.</p><p>　　5.8.1. Timebase</p><p>　　Timebase, generated by 32768Hz, is a combination of frequency sele

50、ctions. The outputs of timebase block are named to TMB1 and TMB2. TMB1 is frequency for TimerA (Clock source B). The TMB1 and TMB2 are the sources for Interrupt (IRQ6). Furthermore, timebases generates additional 2Hz to

51、4096Hz interrupt sources (IRQ4 and IRQ5) for Real-Time-Clock (RTC).</p><p>　　5.9. Sleep, Wakeup and Watchdog</p><p>　　5.9.1. Wakeup and sleep</p><p>　　1) Sleep: After power-on reset

52、, IC starts running until a sleep command occurs. When a sleep command is accepted, IC will turn the system clock (PLL) off. After all, it enters sleep mode.</p><p>　　2) Wakeup: CPU waking up from sleep mode

53、 requires a wakeup signal to turn the system clock (PLL) on. The IRQ signal makes CPU to complete the wakeup process and initialization. The key wakeup and interrupt sources (IRQ1 - IRQ6) can be used for wakeup sources.&

54、lt;/p><p>　　5.9.2. Watchdog</p><p>　　The purpose of watchdog is to monitor if the system operates normally. Within a certain period, watchdog must be cleared. If watchdog is not cleared, CPU assume

55、s the program has been running in an abnormal condition. As a result, the CPU will reset the system to the initial state and start running the program all over again. The watchdog function can be removed by bonding optio

56、n. In SPCE061A, the clear period is 0.75 seconds. If watchdog is cleared within each 0.75 seconds, the system will not b</p><p>　　5.10. ADC (Analog to Digital Converter) / DAC</p><p>　　The SPCE0

57、61A has eight channels 10-bit ADC (Analog to Digital Converter). The function of an ADC is to convert analog signal to digital signal, e.g. a voltage level into a digital word. The eight channels of ADC can be seven chan

58、nels of line-in from IOA [6:0] or one channel microphone (MIC) input through amplifier and AGC controller. The MIC amplifier circuit is capable of reducing common mode noise by transmitting signals through differential M

59、IC Inputs (MICN, MICP). Moreover, an external resis</p><p>　　The SPCE061A has two 10-bit D/A with 2.0mA or 3.0mA driving current for audio outputs, DAC1 and DAC2.</p><p>　　5.11. Serial Interface

60、 I/O (SIO)</p><p>　　Serial interface I/O offers a one-bit serial interface for communication. This serial interface is capable of transmitting or receiving data via two I/O pins, IOB0 (SCK) and IOB1 (SDA).&l

61、t;/p><p>　　5.12. UART</p><p>　　UART block provides a full-duplex standard interface that facilitates the communication with other devices. With this interface, SPCE can transmit and receive simulta

62、neously. The maximum baud-rate can be up to 115200bps. This function can be accomplished by using PortB and Interrupt (UART IRQ). The Rx and Tx of UART are shared with IOB7 and IOB10. When SPCE061A receives and/or transm

63、its a frame of data, the b7 (RxRDY) and/or b6 (TxRDY) in Port_UART_Command2(R) will be set to “1” and the UART IRQ</p><p>　　SPCE061A 32K x 16 語音控制器</p><p><b>　　1. 總述</b></p>&

64、lt;p>　　SPCE061A 是繼μ’nSP?系列產(chǎn)品SPCE500A等之后凌陽科技推出的又一個16位結構的微控制器。與SPCE500A不同的是，在存儲器資源方面考慮到用戶的較少資源的需求以及便于程序調(diào)試等功能，SPCE061A里只內(nèi)嵌32K字的閃存FLASH ROM。較高的處理速度使μ’nSP?能夠非常容易地、快速地處理復雜的數(shù)字信號。因此，與SPCE500A相同，以μ’nSP?為核心的SPCE061A微控制器也適用在數(shù)字語音

65、識別應用領域。</p><p>　　SPCE061A在2.6V~3.6V電壓范圍內(nèi)的工作速度范圍為0.32MHz~49.152MHz，較高的工作速度使其應用領域更加拓寬。2K字SRAM和32K字閃存ROM僅占一頁存儲空間，32位可編程的多功能I/O端口；兩個16位定時器/計數(shù)器；32768Hz實時時鐘；低電壓復位/監(jiān)測功能；8通道10位模-數(shù)轉換輸入功能并具有內(nèi)置自動增益控制功能的麥克風輸入方式；雙通道10位DA

66、C方式的音頻輸出功能。SPCE061A是數(shù)字聲音和語音識別產(chǎn)品的一種最經(jīng)濟的應用。</p><p><b>　　2. 性能</b></p><p>　　? 16位μ’nSP?微處理器；</p><p>　　? 工作電壓：VDD為2.6~3.6V(cpu), VDDH為VDD~5.5V(I/O)；</p><p>　　?

67、CPU時鐘：0.32MHz~49.152MHz ；</p><p>　　? 內(nèi)置2K字SRAM；</p><p>　　? 內(nèi)置32K閃存ROM；</p><p>　　? 可編程音頻處理；</p><p><b>　　? 晶體振蕩器；</b></p><p>　　? 系統(tǒng)處于備用狀態(tài)下(時鐘處于停止

68、狀態(tài))，耗電小于2μA@3.6V；</p><p>　　? 2個16位可編程定時器/計數(shù)器(可自動預置初始計數(shù)值)；</p><p>　　? 2個10位DAC(數(shù)-模轉換)輸出通道；</p><p>　　? 32位通用可編程輸入/輸出端口；</p><p>　　? 14個中斷源可來自定時器A / B，時基，2個外部時鐘源輸入，鍵喚醒；<

69、/p><p>　　? 具備觸鍵喚醒的功能；</p><p>　　? 使用凌陽音頻編碼SACM_S240方式(2.4K位/秒)，能容納210秒的語音數(shù)據(jù)；</p><p>　　? 鎖相環(huán)PLL振蕩器提供系統(tǒng)時鐘信號；</p><p>　　? 32768Hz實時時鐘；</p><p>　　? 7通道10位電壓模-數(shù)轉換器(AD

70、C)和單通道聲音模-數(shù)轉換器</p><p>　　? 聲音模-數(shù)轉換器輸入通道內(nèi)置麥克風放大器和自動增益控制(AGC)功能；</p><p>　　? 具備串行設備接口；</p><p>　　? 低電壓復位(LVR)功能和低電壓監(jiān)測(LVD)功能；</p><p>　　? 內(nèi)置在線仿真板(ICE，In- Circuit Emulator)接口。

71、</p><p><b>　　3. 結構框圖</b></p><p>　　SPCE061A的結構如下圖3.1所示：</p><p><b>　　圖3.1</b></p><p><b>　　4. 應用領域</b></p><p><b>　　?

72、 語音識別類產(chǎn)品</b></p><p>　　? 智能語音交互式玩具</p><p>　　? 高級亦教亦樂類玩具</p><p>　　? 兒童電子故事書類產(chǎn)品</p><p>　　? 通用語音合成器類產(chǎn)品</p><p>　　? 需較長語音持續(xù)時間類產(chǎn)品</p><p><b&

73、gt;　　5. 功能描述</b></p><p><b>　　5.1. CPU</b></p><p>　　SPCE061A配備了凌陽科技開發(fā)的最新的16位微處理器μ’nSP?。它內(nèi)含有8個寄存器：4個通用寄存器R1~R4，1個程序計數(shù)器PC，1個堆棧指針SP，1個基址指針BP和1個段寄存器SR。通用寄存器R3和R4結合形成一個32位寄存器MR，MR可被用

74、作乘法運算和內(nèi)積運算的目標寄存器。此外，SPCE061A有3個FIQ中斷和14個IRQ中斷，并且?guī)в幸粋€由指令BREAK控制的軟中斷。</p><p>　　μ’nSP?不僅可以進行加、減等基本算術運算和邏輯運算，還可以完成用于數(shù)字信號處理的乘法運算和內(nèi)積運算。</p><p><b>　　5.2. 存儲器</b></p><p>　　5.2.1

75、. RAM</p><p>　　SPCE061A擁有2K字的SRAM(包括堆棧區(qū))，其地址范圍從$000000到$0007FF。</p><p>　　5.2.2. 閃存（Flash）ROM</p><p>　　全部32K字閃存均可在ICE工作方式下被編程寫入或被擦除。對閃存設置保密設定后，其內(nèi)容將不能再通過ICE被讀寫，也就可以使程序不被其他人讀取。</p&g

76、t;<p>　　5.3. 時鐘（鎖相環(huán)振蕩器，系統(tǒng)時鐘，實時時鐘）</p><p>　　5.3.1. 鎖相環(huán)(PLL，Phase Lock Loop)振蕩器</p><p>　　PLL的作用是為系統(tǒng)提供一個實時時鐘的基頻(32768Hz)，然后將基頻進行倍頻，調(diào)整至49.152MHz、40.96MHz、32.768MHz、24.576MHz或20.480MHz。系統(tǒng)默認的PL

77、L自激振蕩頻率為24.576MHz。</p><p>　　PLL的結構如下圖5.1所示：</p><p><b>　　圖5.1</b></p><p><b>　　5.3.2. 時鐘</b></p><p>　　5.3.2.1. 系統(tǒng)時鐘</p><p>　　系統(tǒng)時鐘的信號源

78、為PLL振蕩器。系統(tǒng)時鐘頻率(Fosc)和CPU時鐘頻率(CPUCLK)可通過對P_SystemClock(寫)($7013H)單元編程來控制。默認的Fosc、CPUCLK分別為24.576MHz和Fosc/8。用戶可以通過對P_SystemClock單元編程完成對系統(tǒng)時鐘和CPU時鐘頻率的定義。當系統(tǒng)被喚醒后最初時刻的CPUCLK頻率亦為Fosc/8，隨后逐漸被調(diào)整到用戶設定的CPUCLK頻率。這樣，可避免系統(tǒng)在喚醒初始時刻讀ROM出

79、現(xiàn)錯誤。</p><p>　　5.3.2.2. 實時時鐘（32768Hz）</p><p>　　32768Hz實時時鐘通常用于鐘表、實時時鐘延時以及其它與時間相關類產(chǎn)品。SPCE061A通過對32768Hz實時時鐘源分頻而提供了多種實時時鐘中斷源。例如，用作喚醒源的中斷源IRQ5_2Hz，表示系統(tǒng)每隔0.5秒被喚醒一次，由此可作為精確的計時基準。”</p><p>

80、　　除此之外，SPCE061A 還支持RTC振蕩器強振模式/自動模式的轉換。處于強振模式時，RTC振蕩器始終運行在高耗能的狀態(tài)下。處于自動弱振模式時，系統(tǒng)在上電復位后的前7.5s內(nèi)處于強振模式，然后自動切換到弱振模式以降低功耗。</p><p>　　下圖5.2為SPCE061A與晶體振蕩器的連接電路原理圖。</p><p><b>　　圖5.2</b></p&g

81、t;<p><b>　　5.4. 節(jié)電模式</b></p><p>　　SPCE061A可設置節(jié)電的備用模式以達到節(jié)能的目的。在這種工作模式下，只需很小（小于2μA）的備用電流。</p><p>　　要進入待命工作模式，首先應將所需的鍵喚醒口IOA[7~0]設為輸入端口。在進入待命工作模式前，通過讀P_IOA_Latch單元來激活IOA[7~0]口的喚醒

82、功能，或者允許作為喚醒源的中斷源中斷請求的響應；然后通過寫入P_SystemClock單元一個CPUClk STOP控制字（CPU睡眠信號），以停止CPUClk工作，進入‘睡眠’狀態(tài)。P_SystemClock單元還可用來編程設置在CPU進入‘睡眠’時是禁止/允許32768Hz實時時鐘的工作。</p><p>　　在待命模式下，RAM和I/O端口的狀態(tài)都將維持進入‘睡眠’前的各個狀態(tài)，直到產(chǎn)生‘喚醒’信號。SPC

83、E061A的喚醒源包括鍵喚醒IOA[7~0]端口以及各中斷源（IRQ0 ~ IRQ6）。當SPCE061A的CPU被喚醒后，會繼續(xù)執(zhí)行程序指令。</p><p>　　5.5. 低電壓監(jiān)測和低電壓復位</p><p>　　5.5.1. 低電壓監(jiān)測 (LVD，Low Voltage Detect)</p><p>　　低電壓監(jiān)測功能可以提供系統(tǒng)內(nèi)電源電壓的使用情況。4級

84、電壓監(jiān)測低限：2.4V、2.8V、3.2和3.6V，可通過對P_LVD_Ctrl單元編程進行控制。假定VLVD=3.2V，當系統(tǒng)電壓Vcc低于3.2V時，P_LVD_Ctrl單元的第15位返回值為“1”，這樣，CPU可以通過可編程電壓監(jiān)測低限來完成低電壓監(jiān)測。系統(tǒng)默認的電壓監(jiān)測低限為2.4V。</p><p>　　5.5.2. 低電壓復位 (LVR，Low Voltage Reset)</p>&l

85、t;p>　　引起SPCE061A復位通常有2個途徑：電源上電復位、低電壓復位（LVR）。</p><p>　　當電源電壓低于2.2V時，系統(tǒng)會變得不穩(wěn)定且易出故障。導致電源電壓過低的原因很多，如電壓的反跳、負載過重、電池能量不足……。如果系統(tǒng)設置了低電壓復位(LVR)功能，當電源電壓低于該值時，會在4個時鐘周期之后產(chǎn)生一個復位信號，使系統(tǒng)復位。如下圖5.3：</p><p><

86、b>　　圖5.3</b></p><p>　　5.6. 中斷（Interrupt）</p><p>　　SPCE061A具有兩種中斷方式：快速中斷請求FIQ(Fast Interrupt Request)中斷和中斷請求IRQ(Interrupt Request)中斷。中斷控制器可處理3種FIQ中斷和14種IRQ中斷，以及一個由指令BREAK控制的軟中斷。</p>

87、;<p>　　相比之下，F(xiàn)IQ中斷的優(yōu)先級較高而IRQ中斷的優(yōu)先級較低。也就是說，F(xiàn)IQ中斷可以中斷IRQ中斷服務子程序的執(zhí)行，而CPU執(zhí)行相應的FIQ中斷服務子程序的過程不能被任何中斷源的中斷請求中斷。下表1列出了中斷的優(yōu)先級別：</p><p><b>　　表1</b></p><p>　　5.7. 輸入/輸出端口（I/O，Input/Output）

88、</p><p>　　輸入輸出端口是系統(tǒng)與其它設備進行數(shù)據(jù)交換的接口。SPCE061A具有兩個可編程輸入輸出端口：A口和B口。A口既是具有可編程喚醒功能的普通I/O口，又可與ADC的多路LINE_IN輸入共用(IOA[6~0]與LINE_IN[1~7]共用；B口除了具有普通I/O口的功能外，在特定的管腳上還可以完成一些特殊的功能。I/O端口如下圖5.4所示：</p><p><b&g

89、t;　　圖5.4</b></p><p>　　盡管數(shù)據(jù)能通過數(shù)據(jù)端口P_IOX_Data和數(shù)據(jù)緩沖器端口P_IOX_Buffer寫入相同的數(shù)據(jù)寄存器，但從這兩個端口讀出的數(shù)據(jù)卻來自不同的位置；從后者讀出的仍是數(shù)據(jù)寄存器里的數(shù)據(jù)，而從前者讀出的是I/O管腳上的電平狀態(tài)。IOA[7~0]口為鍵喚醒源，通過讀P_IOA_Latch單元來鎖存IOA[7~0]端口的電平狀態(tài)，從而可激活其喚醒功能。當IOA[7~

90、0]口的狀態(tài)和鎖存時的狀態(tài)不一致時，會觸發(fā)系統(tǒng)由節(jié)電的睡眠工作模式切換到喚醒模式。</p><p>　　B口除了具有常規(guī)的輸入/輸出端口功能外，還有一些特殊的功能，如下表2所示：</p><p><b>　　表2</b></p><p>　　如下圖5.5所示的電路顯示了帶有反饋應用的IOB2、IOB3、IOB4和IOB5等端口的設置情況。有了反

91、饋功能，只要在IOB2(IOB3)和IOB4(IOB5)之間增加一個RC電路就可以從EXT1 (EXT2)得到振蕩源頻率信號。</p><p><b>　　圖5.5</b></p><p>　　5.8. 定時器/計數(shù)器（Timer/Counter）</p><p>　　SPCE061A提供了兩個16位的定時器/計數(shù)器：TimerA和TimerB

92、。TimerA為通用計數(shù)器；TimerB為多功能計數(shù)器。TimerA的時鐘源由時鐘源A和時鐘源B進行“與”操作而形成；TimerB的時鐘源僅為時鐘源A。定時器發(fā)生溢出后會產(chǎn)生一個溢出信號(TAOUT/TBOUT)。一方面，它會作為定時器中斷信號傳輸給CPU中斷系統(tǒng)；另一方面，它又會作為4位計數(shù)器計數(shù)的時鐘源信號，輸出一個具有4位可調(diào)的脈寬調(diào)制占空比輸出信號APWMO或BPWMO(分別從IOB8 和IOB9輸出)，用來控制馬達或其它一些設

93、備的速度。此外，定時器溢出信號還可以用于觸發(fā)ADC輸入的自動轉換過程和DAC輸出的數(shù)據(jù)鎖存。</p><p><b>　　表3</b></p><p>　　向定時器的P_TimerA_Data(讀/寫)($700AH)單元或P_TimerB_Data(讀/寫)($700CH)單元寫入一個計數(shù)值N后，選擇一個合適的時鐘源，定時器/計數(shù)器將在所選的時鐘頻率下開始以遞增方式

94、計數(shù)N，N+1，N+2，…0xFFFE，0xFFFF。當計數(shù)達到0xFFFF后，定時器/計數(shù)器溢出，產(chǎn)生中斷請求信號，被CPU響應后送入中斷控制器進行處理。同時，N值將被重新載入定時器/計數(shù)器并重新開始計數(shù)。</p><p>　　在TimerA內(nèi)，時鐘源A是一個高頻時鐘源，時鐘源B是一個低頻時鐘源。時鐘源A和時鐘源B的組合，為TimerA提供出多種計數(shù)速度。若以ClkA作為門控信號，‘1’表示允許時鐘源B信號通過

95、，而‘0’則表示禁止時鐘源B信號通過而停止TimerA的計數(shù)。例如，如果時鐘源A為“1”，TimerA時鐘頻率將取決于時鐘源B；如果時鐘源A為“0”，將停止TimerA的計數(shù)。EXT1和EXT2為外部時鐘源。</p><p>　　下圖5.6為一個3/16的脈寬調(diào)制占空比輸出信號產(chǎn)生過程的時序。APWMO波形是通過寫入P_TimeA_Ctrl 單元的B9~B6選擇一個脈寬數(shù)（以計數(shù)溢出周期數(shù)定義）產(chǎn)生出來的，即每1

96、6個計數(shù)溢出周期將產(chǎn)生一個由上述單元定義的脈寬。此類PWM信號可以用于控制馬達及其它設備的速度。</p><p><b>　　圖5.6</b></p><p>　　一般來說，時鐘源A為高速時鐘源，時鐘源B來自實時時鐘32678Hz系統(tǒng)。因此，時鐘源B能用于一個精確的時間計數(shù)器。例如，2Hz 時鐘信號可用于實時時間計數(shù)。</p><p><

97、b>　　5.8.1. 時基</b></p><p>　　時間基準信號，簡稱時基信號，來自于32768Hz實時時鐘，通過頻率選擇組合而成。時基信號發(fā)生器的2個選頻邏輯TMB1和TMB2為TimerA的時鐘源B提供各種頻率選擇信號并為中斷系統(tǒng)提供中斷源(IRQ6)信號。此外，時基信號發(fā)生器還可以直接生成2Hz、4Hz、1024Hz、2048Hz以及4096Hz的時基信號，為中斷系統(tǒng)提供各種實時中斷源

98、(IRQ4和IRQ5)信號。</p><p><b>　　表4</b></p><p>　　5.9. 睡眠、喚醒</p><p>　　5.9.1. 睡眠與喚醒</p><p>　　1） 睡眠：IC在上電復位開始工作，直到接收到睡眠信號后，才關閉系統(tǒng)時鐘(PLL振蕩器)，進入睡眠狀態(tài)。系統(tǒng)進入睡眠狀態(tài)后，程序計數(shù)器(PC)

99、會停在程序的下一條指令計數(shù)上，當有任一喚醒事件發(fā)生后開始由此繼續(xù)執(zhí)行程序。</p><p>　　2） 喚醒：若要將系統(tǒng)從睡眠狀態(tài)喚醒，需要有喚醒源提供一個喚醒信號來啟動系統(tǒng)時鐘。IRQ中斷請求信號引導CPU完成喚醒過程并將系統(tǒng)初始化。IRQ3_KEY為觸鍵喚醒源(IOA7~0)，其它中斷源(FIQ、IRQ1~IRQ6 及UART IRQ)都可以作為喚醒源。</p><p>　　5.10.

100、模數(shù)轉換器 (ADC,Analog to Digital Converter) 與數(shù)/模轉換器（DAC,Digital to Analog Converter）</p><p>　　SPCE061A有8個10位模-數(shù)轉換器通道，其中7個通道用于將模擬量信號 (例如電壓信號) 轉換為數(shù)字量信號, 可以直接通過引線(IOA[0~6])輸入。另外有一個通道只作為語音輸入通道，通過內(nèi)置有自動增益控制放大器的麥克風通道(M

101、IC_IN)輸入。實際上可以把ADC看作是一個實現(xiàn)模/數(shù)信號轉換的編碼器。</p><p>　　SPCE061A為音頻輸出提供了兩個10位的數(shù)-模轉換器，即DAC1和DAC2。DAC1、DAC2轉換輸出的模擬量電流信號分別通過AUD1和AUD2管腳輸出。</p><p>　　5.11. 串行設備接口（SIO，Serial Input Output）</p><p>

102、　　串行輸入輸出端口SIO提供了一個1位的串行接口，用于與其它設備進行數(shù)據(jù)通訊。在SPCE061A內(nèi)通過IOB0和IOB1這2個端口實現(xiàn)與設備進行串行數(shù)據(jù)交換功能。</p><p>　　5.12. 音頻算法</p><p>　　在SPCE061A中可使用以下幾種語音信號：PCM，LOG PCM，SACM_A3200，SACM_S240，SACM_S480，SACM_S720，SACM_A2

103、000及SACM_A2000_DVR (Digital Voice Recorder)。至于音調(diào)合成，SPCE061A則提供了SACM_MS01 (FM synthesizer)和波表合成器。</p><p>　　5.13. 保密設定</p><p>　　如果希望將內(nèi)部的閃存進行保密設定，可將PFUSE接5V, PVIN接GND并維持2s以上即可將內(nèi)部保險絲熔化，此后就無法再完成downl

104、oad, debug等功能。</p><p>　　5.14. UART</p><p>　　UART模塊提供了一個全雙工標準接口， 用于完成SPCE061A與外設之間的串行通訊(最大的波特率可達115200bps)。借助于IOB口的特殊功能和UART IRQ中斷，可以完成UART接口的通訊功能。此外，SPCE061A還可以接收緩沖器內(nèi)容。也就是說，它可以在讀取緩存器內(nèi)當前數(shù)據(jù)之前接收新的數(shù)