外文翻譯-中英文對照avr單片機(jī)

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1、　　AVR CPU Core　　Introduction This section discusses the AVR core architecture in general. The main function of the　　CPU core is to ensure correct program execution. The

2、CPU must therefore be able to　　access memories, perform calculations, control peripherals, and handle interrupts.　　Architectural Overview Figure 3. Block Diagram of the AVR MCU A

3、rchitecture　　In order to maximize performance and parallelism, the AVR uses a Harvard architecture　　– with separate memories and buses for program and data. Instructions in the p

4、rogram　　memory are executed with a single level pipelining. While one instruction is being executed,　　the next instruction is pre-fetched from the program memory. This concept<

5、;/p>　　enables instructions to be executed in every clock cycle. The program memory is In-　　System Reprogrammable Flash memory.　　The fast-access Register File contai

6、ns 32 x 8-bit general purpose working registers with　　a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU)　　operation. In a typical ALU operatio

7、n, two operands are output from the Register File,　　the operation is executed, and the result is stored back in the Register File – in one　　clock cycle.　　Six

8、 of the 32 registers can be used as three 16-bit indirect address register pointers for　　Data Space addressing – enabling efficient address calculations. One of the these　　addres

9、s pointers can also be used as an address pointer for look up tables in Flash Program　　memory. These added function registers are the 16-bit X-, Y-, and Z-register,　　described la

10、ter in this section.　　The ALU supports arithmetic and logic operations between registers or between a constant　　and a register. Single register operations can also be executed in

11、 the ALU. After　　Flash　　Program　　Memory　　Instruction<b&

12、gt;　　Register　　Instruction　　Decoder　　Program　　Counter<

13、p>　　Control Lines　　32 x 8　　General　　Purpose　　Registrers

14、　　ALU　　Status　　and Control　　I/O Lines　　EEPROM<

15、;p>　　Data Bus 8-bit　　Data　　SRAM　　Direct Addressing　　Indirect Addressing<

16、;b>　　Interrupt　　Unit　　SPI　　Unit　　Watchdog</p

17、>　　Timer　　Analog　　Comparator　　I/O Module 2　　I/O Module1　　I/O Mo

18、dule n　　9　　ATmega16(L)　　2466N–AVR–10/06　　an arithmetic operation, the Status Register is updated to reflect informati

19、on about the　　result of the operation.　　Program flow is provided by conditional and unconditional jump and call instructions,　　able to directly address the w

20、hole address space. Most AVR instructions have a single　　16-bit word format. Every program memory address contains a 16- or 32-bit instruction.　　Program Flash memory space is div

21、ided in two sections, the Boot program section and　　the Application Program section. Both sections have dedicated Lock bits for write and　　read/write protection. The SPM instruct

22、ion that writes into the Application Flash memory　　section must reside in the Boot Program section.　　During interrupts and subroutine calls, the return address Program Counter (P

23、C) is　　stored on the Stack. The Stack is effectively allocated in the general data SRAM, and　　consequently the Stack size is only limited by the total SRAM size and the usage of

24、the　　SRAM. All user programs must initialize the SP in the reset routine (before subroutines　　or interrupts are executed). The Stack Pointer SP is read/write accessible in the I/

25、O　　space. The data SRAM can easily be accessed through the five different addressing　　modes supported in the AVR architecture.　　The memory spaces in the AVR

26、architecture are all linear and regular memory maps.　　A flexible interrupt module has its control registers in the I/O space with an additional　　global interrupt enable bit in th

27、e Status Register. All interrupts have a separate interrupt　　vector in the interrupt vector table. The interrupts have priority in accordance with their　　interrupt vector positio

28、n. The lower the interrupt vector address, the higher the priority.　　The I/O memory space contains 64 addresses for CPU peripheral functions as Control　　Registers, SPI, and other

29、 I/O functions. The I/O Memory can be accessed directly, or as　　the Data Space locations following those of the Register File, $20 - $5F.　　ALU – Arithmetic Logic<p

30、>　　Unit　　The high-performance AVR ALU operates in direct connection with all the 32 general　　purpose working registers. Within a single clock cycle, arithme

31、tic operations between　　general purpose registers or between a register and an immediate are executed. The　　ALU operations are divided into three main categories – arithmetic, lo

32、gical, and bit-functions.　　Some implementations of the architecture also provide a powerful multiplier　　supporting both signed/unsigned multiplication and fractional format. See

33、the “Instruction　　Set” section for a detailed description.　　Status Register The Status Register contains information about the result of the most recently executed<

34、;p>　　arithmetic instruction. This information can be used for altering program flow in order to　　perform conditional operations. Note that the Status Register is updated after all ALU&

35、lt;p>　　operations, as specified in the Instruction Set Reference. This will in many cases　　remove the need for using the dedicated compare instructions, resulting in faster and

36、;　　more compact code.　　The Status Register is not automatically stored when entering an interrupt routine and　　restored when returning from an interrupt. This must be handled by

37、software.　　The AVR Status Register – SREG – is defined as:　　Bit 7 6 5 4 3 2 1 0　　I T H S V N Z C SREG　　Read/Write R/W R/W R/W R/W R/W R/

38、W R/W R/W　　Initial Value 0 0 0 0 0 0 0 0　　10 ATmega16(L)　　2466N–AVR–10/06　　? Bit 7 – I: Global Interrupt Enable　　Th

39、e Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual　　interrupt enable control is then performed in separate control registers. If the Global

40、;　　Interrupt Enable Register is cleared, none of the interrupts are enabled independent of　　the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt&l

41、t;p>　　has occurred, and is set by the RETI instruction to enable subsequent interrupts. The Ibit　　can also be set and cleared by the application with the SEI and CLI instructions, as&l

42、t;p>　　described in the instruction set reference.　　? Bit 6 – T: Bit Copy Storage　　The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or</p

43、>　　destination for the operated bit. A bit from a register in the Register File can be copied　　into T by the BST instruction, and a bit in T can be copied into a bit in a register in th

44、e　　Register File by the BLD instruction.　　? Bit 5 – H: Half Carry Flag　　The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carr

45、y is　　useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.　　? Bit 4 – S: Sign Bit, S = N ⊕ V　　The S-bit is always an exc

46、lusive or between the Negative Flag N and the Two’s Complement　　Overflow Flag V. See the “Instruction Set Description” for detailed information.　　? Bit 3 – V: Two’s Complement Ov

47、erflow Flag　　The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See　　the “Instruction Set Description” for detailed information.　　?

48、Bit 2 – N: Negative Flag　　The Negative Flag N indicates a negative result in an arithmetic or logic operation. See　　the “Instruction Set Description” for detailed information.<

49、;/p>　　? Bit 1 – Z: Zero Flag　　The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the　　“Instruction Set Description” for detailed infor

50、mation.　　? Bit 0 – C: Carry Flag　　The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction　　Set Description” for detailed

51、 information.　　11　　ATmega16(L)　　2466N–AVR–10/06　　General Purpose　　Register File<p

52、>　　The Register File is optimized for the AVR Enhanced RISC instruction set. In order to　　achieve the required performance and flexibility, the following input/output schemes are<p&

53、gt;　　supported by the Register File:　　? One 8-bit output operand and one 8-bit result input　　? Two 8-bit output operands and one 8-bit result input　　? Two 8-

54、bit output operands and one 16-bit result input　　? One 16-bit output operand and one 16-bit result input　　Figure 4 shows the structure of the 32 general purpose working registers

55、 in the CPU.　　Figure 4. AVR CPU General Purpose Working Registers　　Most of the instructions operating on the Register File have direct access to all registers,<p&g

56、t;　　and most of them are single cycle instructions.　　As shown in Figure 4, each register is also assigned a data memory address, mapping　　them directly into the first 32 location

57、s of the user Data Space. Although not being physically　　implemented as SRAM locations, this memory organization provides great　　flexibility in access of the registers, as the X-

58、, Y-, and Z-pointer Registers can be set to　　index any register in the file.　　7 0 Addr.　　R0 $00<

59、;b>　　R1 $01　　R2 $02　　…　　R13 $0D　　General R14 $0E<p&

60、gt;　　Purpose R15 $0F　　Working R16 $10　　Registers R17 $11　　…　　R26 $1A X-register Low Byte　　R27 $1

61、B X-register High Byte　　R28 $1C Y-register Low Byte　　R29 $1D Y-register High Byte　　R30 $1E Z-register Low Byte　　R31 $1F Z-register High

62、Byte　　12 ATmega16(L)　　2466N–AVR–10/06　　The X-register, Y-register and　　Z-register　　The registers R26..R31 have some

63、 added functions to their general purpose usage.　　These registers are 16-bit address pointers for indirect addressing of the Data Space.　　The three indirect address registers X,

64、Y, and Z are defined as described in Figure 5.　　Figure 5. The X-, Y-, and Z-registers　　In the different addressing modes these address registers have functions as fixed displacem

65、ent,　　automatic increment, and automatic decrement (see the Instruction Set　　Reference for details).　　Stack Pointer The Stack is mainly used for storing temp

66、orary data, for storing local variables and for　　storing return addresses after interrupts and subroutine calls. The Stack Pointer Register　　always points to the top of the Stack

67、. Note that the Stack is implemented as growing　　from higher memory locations to lower memory locations. This implies that a Stack　　PUSH command decreases the Stack Pointer. If s

68、oftware reads the Program Counter　　from the Stack after a call or an interrupt, unused bits (15:13) should be masked out.　　The Stack Pointer points to the data SRAM Stack area wh

69、ere the Subroutine and Interrupt　　Stacks are located. This Stack space in the data SRAM must be defined by the　　program before any subroutine calls are executed or interrupts are

70、 enabled. The Stack　　Pointer must be set to point above $60. The Stack Pointer is decremented by one when　　data is pushed onto the Stack with the PUSH instruction, and it is decr

71、emented by two　　when the return address is pushed onto the Stack with subroutine call or interrupt. The　　Stack Pointer is incremented by one when data is popped from the Stack wi

72、th the POP　　instruction, and it is incremented by two when data is popped from the Stack with return　　from subroutine RET or return from interrupt RETI.　　The

73、 AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number　　of bits actually used is implementation dependent. Note that the data space in some　　implem

74、entations of the AVR architecture is so small that only SPL is needed. In this　　case, the SPH Register will not be present.　　15 XH XL 0　　X - register 7 07 0&

75、lt;/p>　　R27 ($1B) R26 ($1A)　　15 YH YL 0　　Y - register 7 07 0　　R29 ($1D) R28 ($1C)　　15 ZH ZL 0　　Z - re

76、gister 7 0 7 0　　R31 ($1F) R30 ($1E)　　Bit 15 14 13 12 11 10 9 8　　SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH　　SP7 SP6 SP5 SP4 SP3 SP2 SP1 S

77、P0 SPL　　7 6 5 4 3 2 1 0　　Read/Write R/W R/W R/W R/W R/W R/W R/W R/W　　R/W R/W R/W R/W R/W R/W R/W R/W　　Initial Value 0 0 0 0 0 0 0 0</

78、p>　　0 0 0 0 0 0 0 0　　13　　ATmega16(L)　　2466N–AVR–10/06　　Instruction Execution<b&

79、gt;　　Timing　　This section describes the general access timing concepts for instruction execution. The　　AVR CPU is driven by the CPU clock clkCPU, directly generated fro

80、m the selected clock　　source for the chip. No internal clock division is used.　　Figure 6 shows the parallel instruction fetches and instruction executions enabled by the

81、;　　Harvard architecture and the fast-access Register File concept. This is the basic pipelining　　concept to obtain up to 1 MIPS per MHz with the corresponding unique results for

82、　　functions per cost, functions per clocks, and functions per power-unit.　　Figure 6. The Parallel Instruction Fetches and Instruction Executions　　Figure 7 shows the int

83、ernal timing concept for the Register File. In a single clock cycle　　an ALU operation using two register operands is executed, and the result is stored back　　to the destination r

84、egister.　　Figure 7. Single Cycle ALU Operation　　Reset and Interrupt　　Handling　　The AVR provides several different int

85、errupt sources. These interrupts and the separate　　reset vector each have a separate program vector in the program memory space. All　　interrupts are assigned individual enable bi

86、ts which must be written logic one together　　with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.　　Depending on the Program Counter value

87、, interrupts may be automatically disabled　　when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software　　security. See the section “Memory Programming” on p

88、age 262 for details.　　The lowest addresses in the program memory space are by default defined as the Reset　　and Interrupt Vectors. The complete list of vectors is shown in “Inter

89、rupts” on page 45.　　The list also determines the priority levels of the different interrupts. The lower the　　address the higher is the priority level. RESET has the highest prior

90、ity, and next is INT0　　clk　　1st Instruction Fetch　　1st Instruction Execute　　2nd Instruction Fetch

91、;　　2nd Instruction Execute　　3rd Instruction Fetch　　3rd Instruction Execute　　4th Instruction Fetch　　T1 T2 T3 T4<b

92、>　　CPU　　Total Execution Time　　Register Operands Fetch　　ALU Operation Execute　　Result Write Back　　T1 T2

93、 T3 T4　　clkCPU　　14 ATmega16(L)　　2466N–AVR–10/06　　– the External Interrupt Request 0. The Interrupt Vectors can be mov

94、ed to the start of　　the Boot Flash section by setting the IVSEL bit in the General Interrupt Control Register　　(GICR). Refer to “Interrupts” on page 45 for more information. The

95、Reset Vector can　　also be moved to the start of the boot Flash section by programming the BOOTRST　　Fuse, see “Boot Loader Support – Read-While-Write Self-Programming” on page 249

96、.　　When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts　　are disabled. The user software can write logic one to the I-bit to enable nested in

97、terrupts.　　All enabled interrupts can then interrupt the current interrupt routine. The I-bit is　　automatically set when a Return from Interrupt instruction – RETI – is executed.

98、　　There are basically two types of interrupts. The first type is triggered by an event that　　sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the

99、　　actual Interrupt Vector in order to execute the interrupt handling routine, and hardware　　clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writin

100、g a　　logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the　　corresponding interrupt enable bit is cleared, the Interrupt Flag will be se

101、t and remembered　　until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or　　more interrupt conditions occur while the Global Interrupt Enable bit

102、is cleared, the corresponding　　Interrupt Flag(s) will be set and remembered until the global interrupt enable　　bit is set, and will then be executed by order of priority.</p&g

103、t;　　The second type of interrupts will trigger as long as the interrupt condition is present.　　These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappea

104、rs　　before the interrupt is enabled, the interrupt will not be triggered.　　When the AVR exits from an interrupt, it will always return to the main program and execute

105、　　one more instruction before any pending interrupt is served.　　Note that the Status Register is not automatically stored when entering an interrupt routine,　　nor restor

106、ed when returning from an interrupt routine. This must be handled by　　software.　　When using the CLI instruction to disable interrupts, the interrupts will be i

107、mmediately　　disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously　　with the CLI instruction. The following example shows how this ca

108、n be used to　　avoid interrupts during the timed EEPROM write sequence.　　Assembly Code Example　　in r16, SREG ; store SREG value　　cli ; di

109、sable interrupts during timed sequence　　sbi EECR, EEMWE ; start EEPROM write　　sbi EECR, EEWE　　out SREG, r16 ; restore SREG value (I-bit)

110、　　C Code Example　　char cSREG;　　cSREG = SREG; /* store SREG value */　　/* disable interrupts during timed sequence */　　_CLI();<

111、;/b>　　EECR |= (1<<EEMWE); /* start EEPROM write */　　EECR |= (1<<EEWE);　　SREG = cSREG; /* restore SREG value (I-bit) */<

112、;b>　　15　　ATmega16(L)　　2466N–AVR–10/06　　When using the SEI instruction to enable interrupts, the instruction following SEI will be<

113、;p>　　executed before any pending interrupts, as shown in this example.　　Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles

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