at89s52單片機應用中英文翻譯

1、<p>　　本科畢業(yè)設計（論文）</p><p>　　AT89S52單片機應用中英文翻譯</p><p>　　專業(yè)名稱： 電氣工程及其自動化 </p><p>　　年級班級： </p><p>　　學生姓名： </p><p>　　指導老師

2、： </p><p>　　河南理工大學電氣學院</p><p><b>　　二O一二年六月九日</b></p><p>　　AT89S52 MCU Applications</p><p>　　Function Characteristic Description</p>&

3、lt;p>　　The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology

4、and is compatible with the indus-try-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory pro-grammer. By combining a

5、 versatile 8-bit CPU with in-system programmable Flash on a monolithic</p><p>　　Pin Description</p><p>　　VCC ：Supply voltage.</p><p>　　GND ：Ground.</p><p>　　Port 0：Port

6、 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to

7、 be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the cod

8、e bytes dur-ing program verification. External pu</p><p>　　Port 1：Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are writ

9、ten to Port 1 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. In add

10、ition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger inpu</p><p>　　Table 1 The second function of the P1 port</p><p>　

11、　Port 2：Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the inter-nal pull-ups and

12、can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program

13、 memory and dur-ing accesses to external data memory that use</p><p>　　Port 3：Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When

14、 1s are written to Port 3 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Por

15、t 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT</p><p>　　Table 2 The second function of the P3 port</p>

16、<p>　　RST：Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives high for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SF

17、R AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled.</p><p>　　ALE/：Address Latch Enable (ALE) is an output pulse for latching t

18、he low byte of the address during accesses to external memory. This pin is also the program pulse input () during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency

19、and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped dur-ing each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR l</

20、p><p>　?。篜rogram Store Enable () is the read strobe to external program memory. When the AT89S52 is executing code from external program memory, is activated twice each machine cycle, except that two activati

21、ons are skipped during each access to exter-nal data memory.</p><p>　　/VPP：External Access Enable. must be strapped to GND in order to enable the device to fetch code from external program memory locations

22、starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, will be internally latched on reset. should be strapped to VCC for internal program executions. This pin also receives the 12-volt program

23、ming enable voltage (VPP) during Flash programming.</p><p>　　XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit.</p><p>　　XTAL2：Output from the i

24、nverting oscillator amplifier.</p><p>　　Program Memory</p><p>　　If the pin is connected to GND, all program fetches are directed to external memory. On the AT89S52, if is connected to VCC, pro

25、gram fetches to addresses 0000H through 1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are to external memory.</p><p>　　Data Memory</p><p>　　The AT89S52 imple

26、ments 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. This means that the upper 128 bytes have the same addresses as the SFR space but are physically separ

27、ate from SFR space. When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructio

28、ns which use direct addressing access the S</p><p>　　Watchdog Timer</p><p>　　The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT con

29、sists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location

30、 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock f</p><p>　　In Power-down mode the oscillator

31、stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external interrup

32、t which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the AT89S52 is reset. Exiting Power-down with an interrupt

33、is significantly different</p><p>　　Timer 0 and 1</p><p>　　Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and Timer 1 in the AT89C51 and AT89C52. For further information on t

34、he timers’ operation, please click on the document link below:</p><p>　　http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF</p><p><b>　　Timer 2</b></p><p>　　Ti

35、mer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/ in the SFR T2CON. Timer 2 has three operating modes: capture, auto-reload (up or down co

36、unting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 6-1. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine

37、 cycle. Since a machine cycle consists of 12 oscillator pe</p><p>　　Table3 Timer 2 Operating Modes</p><p>　　In the Counter function, the register is incremented in response to a 1-to-0 transiti

38、on at its corre-sponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is inc

39、remented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are require</p><p>　　In

40、terrupts</p><p>　　The AT89S52 has a total of six interrupt vectors: two external interrupts ( and ), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. Each of these interrupt source

41、s can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once. Note that bit position IE.6 is uni

42、mplemented. User software should not write a 1 to this bit position, since it may be used i</p><p>　　Oscillator Characteristics</p><p>　　XTAL1 and XTAL2 are the input and output, respectively, o

43、f an inverting amplifier that can be configured for use as an on-chip oscillator. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnec

44、ted while XTAL1 is driven,. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clock-ing circuitry is through a divide-by-two flip-flop, but minimum and maximum volt

45、age</p><p>　　Power-down Mode</p><p>　　In the Power-down mode, the oscillator is stopped, and the instruction that invokes Power-down is the last instruction executed. The on-chip RAM and Special

46、 Function Registers retain their values until the Power-down mode is terminated. Exit from Power-down mode can be initiated either by a hardware reset or by an enabled external interrupt. Reset redefines the SFRs but doe

47、s not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and mus</p><p><b>　　Idle Mod</b></p><p>　　In idle mode, the CPU p

48、uts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions regis-ters remain unchanged during this mode. The idle mo

49、de can be terminated by any enabled interrupt or by a hardware reset. Note that when idle mode is terminated by a hardware reset, the device normally resumes pro-gram execution from where it left off, up to two machine c

50、ycles before the internal reset algor</p><p>　　AT89S52單片機應用</p><p><b>　　功能特征描述</b></p><p>　　AT89S52是一種低功耗、高性能CMOS8位微控制器，具有8K 在系統(tǒng)可編程Flash 存儲器。使用Atmel 公司高密度非易失性存儲器技術(shù)制造，與工業(yè)

51、80C51 產(chǎn)品指令和引腳完全兼容。片上Flash允許程序存儲器在系統(tǒng)可編程，亦適于常規(guī)編程器。在單芯片上，擁有靈巧的8 位CPU 和在系統(tǒng)可編程Flash，使得AT89S52為眾多嵌入式控制應用系統(tǒng)提供高靈活、超有效的解決方案。 AT89S52具有以下標準功能： 8k字節(jié)Flash，256字節(jié)RAM，32 位I/O 口線，看門狗定時器，2個數(shù)據(jù)指針，三個16 位定時器/計數(shù)器，一個6向量2級中斷結(jié)構(gòu)，全雙工串行口，片內(nèi)晶振及時鐘電

52、路。另外，AT89S52 可降至0Hz 靜態(tài)邏輯操作，支持2種軟件可選擇節(jié)電模式。空閑模式下，CPU停止工作，允許RAM、定時器/計數(shù)器、串口、中斷繼續(xù)工作。掉電保護方式下，RAM內(nèi)容被保存，振蕩器被凍結(jié)，單片機一切工作停止，直到下一個中斷或硬件復位為止。</p><p><b>　　引腳描述</b></p><p><b>　　VCC ：電源。</b

53、></p><p><b>　　GND: 接地。</b></p><p>　　P0口： P0口是一個8位漏極開路的雙向I/O口。作為輸出口，每位能驅(qū)動8個TTL邏輯電平。對P0端口寫“1”時，引腳用作高阻抗輸入。當訪問外部程序和數(shù)據(jù)存儲器時，P0口也被作為低8位地址/數(shù)據(jù)復用。在這種模式下，P0具有內(nèi)部上拉電阻。在flash編程時，P0口也用來接收指令字節(jié)；在程

54、序校驗時，輸出指令字節(jié)。程序校驗時，需要外部上拉電阻。</p><p>　　P1口：P1 口是一個具有內(nèi)部上拉電阻的8 位雙向I/O 口，p1 輸出緩沖器能驅(qū)動4 個TTL 邏輯電平。對P1 端口寫“1”時，內(nèi)部上拉電阻把端口拉高，此時可以作為輸入口使用。作為輸入使用時，被外部拉低的引腳由于內(nèi)部電阻的原因，將輸出電流（IIL）。此外，P1.0和P1.2分別作定時器/計數(shù)器2的外部計數(shù)輸入（P1.0/T2）和時器/

55、計數(shù)器2的觸發(fā)輸入（P1.1/T2EX），具體如下表1所示。在flash編程和校驗時，P1口接收低8位地址字節(jié)。</p><p>　　P2口：P2 口是一個具有內(nèi)部上拉電阻的8 位雙向I/O 口，P2 輸出緩沖器能驅(qū)動4 個TTL 邏輯電平。對P2 端口寫“1”時，內(nèi)部上拉電阻把端口拉高，此時可以作為輸入口使用。作為輸入使用時，被外部拉低的引腳由于內(nèi)部電阻的原因，將輸出電（IIL）。在訪問外部程序存儲器或用16位

56、地址讀取外部數(shù)據(jù)存儲器（例如執(zhí)行MOVX @DPTR）時，P2 口送出高八位地址。在這種應用中，P2 口使用很強的內(nèi)部上拉發(fā)送1。在使用8位地址（如MOVX @RI）訪問外部數(shù)據(jù)存儲器時，P2口輸出P2鎖存器的內(nèi)容。在flash編程和校驗時，P2口也接收高8位地址字節(jié)和一些控制信號。</p><p>　　表1 P1口第二功能</p><p>　　表2 P3口第二功能</p>

57、<p>　　P3口：P3 口是一個有內(nèi)部上拉電阻的8 位雙向I/O 口，p2 輸出緩沖器能驅(qū)動4 個TTL 邏輯電平。對P3 端口寫“1”時，內(nèi)部上拉電阻把端口拉高，此時可以作為輸入口使用。作為輸入使用時，被外部拉低的引腳由于內(nèi)部電阻的原因，將輸出電流（IIL）。P3口亦作為AT89S52特殊功能（第二功能）使用，如2表所示。在flash編程和校驗時，P3口也接收一些控制信號。</p><p>　　RS

58、T：復位輸入。晶振工作時，RST腳持續(xù)2 個機器周期高電平將使單片機復位?？撮T狗計時完成后，RST 腳輸出96 個晶振周期的高電平。特殊寄存器AUXR(地址8EH)上的DISRTO位可以使此功能無效。DISRTO默認狀態(tài)下，復位高電平有效。</p><p>　　ALE/：地址鎖存控制信號（ALE）是訪問外部程序存儲器時，鎖存低8 位地址的輸出脈沖。在flash編程時，此引腳()也用作編程輸入脈沖。在一般情況下，A

59、LE 以晶振六分之一的固定頻率輸出脈沖，可用來作為外部定時器或時鐘使用。然而，特別強調(diào)，在每次訪問外部數(shù)據(jù)存儲器時，ALE脈沖將會跳過。如果需要，通過將地址為8EH的SFR的第0位置 “1”，ALE操作將無效。這一位置 “1”，ALE 僅在執(zhí)行MOVX 或MOVC指令時有效。否則，ALE 將被微弱拉高。這個ALE 使能標志位（地址為8EH的SFR的第0位）的設置對微控制器處于外部執(zhí)行模式下無效。</p><p>

60、　?。和獠砍绦虼鎯ζ鬟x通信號()是外部程序存儲器選通信號。當AT89S52從外部程序存儲器執(zhí)行外部代碼時，在每個機器周期被激活兩次，而在訪問外部數(shù)據(jù)存儲器時，將不被激活。</p><p>　　/VPP：訪問外部程序存儲器控制信號。為使能從0000H 到FFFFH的外部程序存儲器讀取指令，必須接GND。為了執(zhí)行內(nèi)部程序指令，應該接VCC。在flash編程期間，也接收12伏VPP電壓。</p><

61、p>　　XTAL1：振蕩器反相放大器和內(nèi)部時鐘發(fā)生電路的輸入端。</p><p>　　XTAL2：振蕩器反相放大器的輸出端。</p><p><b>　　程序存儲器</b></p><p>　　如果引腳接地，程序讀取只從外部存儲器開始。對于89S52，如果 接VCC，程序讀寫先從內(nèi)部存儲器（地址為0000H～1FFFH）開始，接著從外部尋

62、址，尋址地址為：2000H~FFFFH。</p><p><b>　　數(shù)據(jù)存儲器</b></p><p>　　AT89S52 有256 字節(jié)片內(nèi)數(shù)據(jù)存儲器。高128 字節(jié)與特殊功能寄存器重疊。也就是說高128字節(jié)與特殊功能寄存器有相同的地址，而物理上是分開的。當一條指令訪問高于7FH 的地址時，尋址方式?jīng)Q定CPU 訪問高128 字節(jié)RAM 還是特殊功能寄存器空間。直接

63、尋址方式訪問特殊功能寄存器（SFR）。例如，下面的直接尋址指令訪問0A0H（P2口）存儲單元MOV 0A0H , #data。使用間接尋址方式訪問高128 字節(jié)RAM。例如，下面的間接尋址方式中，R0 內(nèi)容為0A0H，訪問的是地址0A0H的寄存器，而不是P2口（它的地址也是0A0H）。MOV @R0 , #data。堆棧操作也是簡介尋址方式。因此，高128字節(jié)數(shù)據(jù)RAM也可用于堆?？臻g。</p><p><

64、b>　　看門狗定時器</b></p><p>　　WDT是一種需要軟件控制的復位方式。WDT 由13位計數(shù)器和特殊功能寄存器中的看門狗定時器復位存儲器（WDTRST）構(gòu)成。WDT 在默認情況下無法工作；為了激活WDT，戶用必須往WDTRST 寄存器（地址：0A6H）中依次寫入01EH 和0E1H。當WDT激活后，晶振工作，WDT在每個機器周期都會增加。WDT計時周期依賴于外部時鐘頻率。除了復位（

65、硬件復位或WDT溢出復位），沒有辦法停止WDT工作。當WDT溢出，它將驅(qū)動RSR引腳一個高個電平輸出。</p><p>　　在掉電模式下，晶振停止工作，這意味這WDT也停止了工作。在這種方式下，用戶不必喂狗。有兩種方式可以離開掉電模式：硬件復位或通過一個激活的外部中斷。通過硬件復位退出掉電模式后，用戶就應該給WDT 喂狗，就如同通常AT89S52 復位一樣。通過中斷退出掉電模式的情形有很大的不同。中斷應持續(xù)拉低很

66、長一段時間，使得晶振穩(wěn)定。當中斷拉高后，執(zhí)行中斷服務程序。為了防止WDT在中斷保持低電平的時候復位器件，WDT 直到中斷拉低后才開始工作。這就意味著WDT 應該在中斷服務程序中復位。為了確保在離開掉電模式最初的幾個狀態(tài)WDT不被溢出，最好在進入掉電模式前就復WDT。在進入待機模式前，特殊寄存器AUXR的WDIDLE位用來決定WDT是否繼續(xù)計數(shù)。默認狀態(tài)下，在待機模式下，WDIDLE＝0，WDT繼續(xù)計數(shù)。為了防止WDT在待機模式下復位AT

67、89S52，用戶應該建立一個定時器，定時離開待機模式，喂狗，再重新進入待機模式。</p><p><b>　　定時器0和定時器1</b></p><p>　　在AT89S52 中，定時器0 和定時器1 的操作與AT89C51 和AT89C52 一樣。為了獲得更深入的關(guān)于UART 的信息，可參考ATMEL 網(wǎng)站（http://www.atmel.com）。從這個主頁，選

68、擇“Products”，然后選擇“8051-Architech Flash Microcontroller”，再選擇“Product Overview”即可。</p><p><b>　　定時器2</b></p><p>　　定時器2是一個16位定時/計數(shù)器，它既可以做定時器，又可以做事件計數(shù)器。其工作方式由特殊寄存器T2CON中的C/T2位選擇（如表2所示）。定時器

69、2有三種工作模式：捕捉方式、自動重載（向下或向上計數(shù)）和波特率發(fā)生器。如表3 所示，工作模式由T2CON中的相關(guān)位選擇。定時器2 有2 個8位寄存器：TH2和TL2。在定時工作方式中，每個機器周期，TL2 寄存器都會加1。由于一個機器周期由12 個晶振周期構(gòu)成，因此，計數(shù)頻率就是晶振頻率的1/12。</p><p>　　表3 定時器2工作模式</p><p>　　在計數(shù)工作方式下，寄存器

70、在相關(guān)外部輸入角T2 發(fā)生1 至0 的下降沿時增加1。在這種方式下，每個機器周期的S5P2期間采樣外部輸入。一個機器周期采樣到高電平，而下一個周期采樣到低電平，計數(shù)器將加1。在檢測到跳變的這個周期的S3P1 期間，新的計數(shù)值出現(xiàn)在寄存器中。因為識別1－0的跳變需要2個機器周期（24個晶振周期），所以，最大的計數(shù)頻率不高于晶振頻率的1/24。為了確保給定的電平在改變前采樣到一次，電平應該至少在一個完整的機器周期內(nèi)保持不變。</p&g

71、t;<p><b>　　中斷</b></p><p>　　AT89S52 有6個中斷源：兩個外部中斷（ 和），三個定時中斷（定時器0、1、2）和一個串行中斷。每個中斷源都可以通過置位或清除特殊寄存器IE 中的相關(guān)中斷允許控制位分別使得中斷源有效或無效。IE還包括一個中斷允許總控制位EA，它能一次禁止所有中斷。IE.6位是不可用的。對于AT89S52，IE.5位也是不能用的。用戶

72、軟件不應給這些位寫1。它們?yōu)锳T89系列新產(chǎn)品預留。定時器2可以被寄存器T2CON中的TF2和EXF2的或邏輯觸發(fā)。程序進入中斷服務后，這些標志位都可以由硬件清0。實際上，中斷服務程序必須判定是否是TF2 或EXF2激活中斷，標志位也必須由軟件清0。定時器0和定時器1標志位TF0 和TF1在計數(shù)溢出的那個周期的S5P2被置位。它們的值一直到下一個周期被電路捕捉下來。然而，定時器2 的標志位TF2 在計數(shù)溢出的那個周期的S2P2被置位，在

73、同一個周期被電路捕捉下來。</p><p><b>　　晶振特性</b></p><p>　　AT89S52 單片機有一個用于構(gòu)成內(nèi)部振蕩器的反相放大器，XTAL1 和XTAL2 分別是放大器的輸入、輸出端。石英晶體和陶瓷諧振器都可以用來一起構(gòu)成自激振蕩器。從外部時鐘源驅(qū)動器件的話，XTAL2 可以不接，而從XTAL1 接入。由于外部時鐘信號經(jīng)過二分頻觸發(fā)后作為外部時

74、鐘電路輸入的，所以對外部時鐘信號的占空比沒有其它要求，最長低電平持續(xù)時間和最少高電平持續(xù)時間等還是要符合要求的。</p><p><b>　　掉電模式</b></p><p>　　在掉電模式下，晶振停止工作，激活掉電模式的指令是最后一條執(zhí)行指令。片上RAM和特殊功能寄存器保持原值，直到掉電模式終止。掉電模式可以通過硬件復位和外部中斷退出。復位重新定義了SFR 的值，但

75、不改變片上RAM 的值。在VCC未恢復到正常工作電壓時，硬件復位不能無效，并且應保持足夠長的時間以使晶振重新工作和初始化。</p><p><b>　　空閑模式</b></p><p>　　在空閑工作模式下，CPU 處于睡眠狀態(tài)，而所有片上外部設備保持激活狀態(tài)。這種狀態(tài)可以通過軟件產(chǎn)生。在這種狀態(tài)下，片上RAM和特殊功能寄存器的內(nèi)容保持不變?？臻e模式可以被任一個中斷或