【中英雙語】179關(guān)于單片機(jī)計(jì)算機(jī)程序網(wǎng)絡(luò)安全有關(guān)的外文文獻(xiàn)翻譯成品：運(yùn)用物理隨機(jī)函數(shù)設(shè)計(jì)和實(shí)現(xiàn)aegis（神盾）單片機(jī)安全處理器（對(duì)照）4萬字符

1、此文檔是畢業(yè)設(shè)計(jì)外文翻譯成品（ 含英文原文+中文翻譯），無需調(diào)整復(fù)雜的格式！下載之后直接可用，方便快捷！本文價(jià)格不貴,也就幾十塊錢！一輩子也就一次的事！外文標(biāo)題：Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions外文作者：G. Edward Suh, Charles W. O’Donnell

2、, Ishan Sachdev, and Srinivas Devadas文獻(xiàn)出處: International Symposium on Computer Architecture (ISCA'05)，2005 (如覺得年份太老，可改為近 2 年，畢竟很多畢業(yè)生都這樣做)英文 9169 單詞，49797 字符，中文 15005 漢字。Design and Implementation of the AEGIS Si

3、ngle-Chip Secure Processor Using Physical Random FunctionsABSTRACT:Secure processors enable new applications by ensuring private and authentic program execution even in the face of physical attack. In this paper we pres

4、ent the AEGIS secure processor architecture, and evaluate its RTL implementation on FPGAs. By using Physical Random Functions, we propose a new way of reliably protecting and sharing secrets that is more secure than exis

5、ting solutions based on non-volatile memory. Our architecture gives applications the flexibility of trusting and protecting only a portion of a given process, unlike prior proposals which require a process to be protecte

6、d in entirety. We also put forward a specific model of how secure applications can be programmed in a high-level language and compiled to run on our system. Finally, we evaluate a fully functional FPGA implementation of

7、our processor, assess the implementation tradeoffs, compare performance, and demonstrate the benefits of partially protecting a program.physical attacks.We present in this paper the AEGIS single-chip secure processor arc

8、hitecture which uses Physical Random Functions (or Physical Unclonable Functions, PUFs), to veritably create and maintain secure secrets. PUFs have been previously proposed in [5]. We show how to use a PUF for reliable s

9、ecret generation and how to use PUF secrets to design and build a secure processor.Our secure processor architecture is able to provide the secure environments mentioned which are necessary for trusted and private comput

10、ation. To guarantee a tamper-evident environment, our processor protects against physical attacks on memory and prevents any physical or digital tampering of programs before their execution. Physical memory tampering is

11、precluded by a hardware integrity verification algorithm, and private tamper-resistant execution maintains privacy through efficient on-chip memory encryption and decryption methods. Other software attacks are countered

12、with architectural modifications to the processor governing access rights, which are under the control of a security kernel.Moreover, unlike prior secure architecture proposals, our processor does not require that an app

13、lication remain in a secure execution environment at all times. We have added a new suspended secure environment, which is an environment that can be switched to from within a secure environment to allow tamper-evident o

14、r tamper- resistant state to persist in suspension while unprotected program code is executed. This unprotected execution is prohibited from accessing anything belonging to the secure environment, and is required to retu

15、rn control flow to a specific program location.A suspended secure environment enables applications to have a more flexible trust model. For example, it allows applications to integrate library and API functionality into

16、their program without requiring those libraries to be verifiably trusted. As it is commonly the case that only small regions of code need to be trusted to achieve the security requirements of the entire application, this