外文翻譯--三位半lcdled顯示ad轉(zhuǎn)換器

1、<p><b>　　中文3390字</b></p><p>　　Digit, LCD/LED Display, A/D Converters</p><p>　　Abstract: The Intersil ICL7106 and ICL7107 are high performance, low power, digit A/D converters. I

2、ncluded are seven segment decoders, display drivers, a reference, and a clock. The ICL7106 is designed to interface with a liquid crystal display (LCD) and includes a multiplexed backplane drive; the ICL7107 will directl

3、y drive an instrument size light emitting diode (LED) display. </p><p>　　The ICL7106 and ICL7107 bring together a combination of high accuracy, versatility, and true economy. It features autozero to less tha

4、n 10μV, zero drift of less than 1μV/℃, input bias current of 10pA (Max), and rollover error of less than one count. True differential inputs and reference are useful in all systems, but give the designer an uncommon adva

5、ntage when measuring load cells, strain gauges and other bridge type transducers. Finally, the true economy of single power supply operation (ICL7</p><p>　　Keyword: Digit LCD/LED Display A/D Converte

6、rs</p><p>　　1 Features</p><p>　　(1)Guaranteed Zero Reading for 0V Input on All Scales</p><p>　　(2)1pA Typical Input Current</p><p>　　(3)True Differential Input and Refe

7、rence, Direct Display Drive -LCD ICL7106, LED LCL7107</p><p>　　(4)Low Noise - Less Than 15μVP-P</p><p>　　(5)On Chip Clock and Reference</p><p>　　(6)Low Power Dissipation - Typically

8、 Less Than 10mW</p><p>　　(7)No Additional Active Circuits Required</p><p>　　2 Detailed Description</p><p>　　2.1 Analog Section</p><p>　　Figure 1 shows the Analog Sectio

9、n for the ICL7106 and ICL7107. Each measurement cycle is divided into three phases. They are (1) auto-zero (A-Z), (2) signal integrate (INT) and (3) de-integrate (DE).</p><p>　　FIGURE 1 ANALOG SECTION OF ICL

10、7106 AND ICL7107</p><p>　　2.2 Auto-Zero Phase</p><p>　　During auto-zero three things happen. First, input high and low are disconnected from the pins and internally shorted to analog COMMON. Sec

11、ond, the reference capacitor is charged to the reference voltage. Third, a feedback loop is closed around the system to charge the auto-zero capacitor CAZ to compensate for offset voltages in the buffer amplifier, integr

12、ator, and comparator. Since the comparator is included in the loop, the AZ accuracy is limited only by the noise of the system. In any case, </p><p>　　2.3 Signal Integrate Phase</p><p>　　During

13、signal integrate, the auto-zero loop is opened, the internal short is removed, and the internal input high and low are connected to the external pins. The converter then integrates the differential voltage between IN HI

14、and IN LO for a fixed time. This differential voltage can be within a wide common mode range: up to 1V from either supply. If, on the other hand, the input signal has no return with respect to the converter power supply,

15、 IN LO can be tied to analog COMMON to establish the </p><p>　　2.4 De-Integrate Phase</p><p>　　The final phase is de-integrate, or reference integrate. Input low is internally connected to analo

16、g COMMON and input high is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to r

17、eturn to zero. The time required for the output to return to zero is proportional to the input signal. Specifically the digital reading displayed is:</p><p>　　DISPLAY COUNT=</p><p>　　2.5 Differe

18、ntial Input</p><p>　　The input can accept differential voltages anywhere within the common mode range of the input amplifier, or specifically from 0.5V below the positive supply to 1V above the negative supp

19、ly. In this range, the system has a CMRR of 86dB typical. However, care must be exercised to assure the integrator output does not saturate. A worst case condition would be a large positive common mode voltage with a nea

20、r full scale negative differential input voltage. The negative input signal drives the integra</p><p>　　2.6 Differential Reference</p><p>　　The reference voltage can be generated anywhere within

21、 the power supply voltage of the converter. The main source of common mode error is a roll-over voltage caused by the reference capacitor losing or gaining charge to stray capacity on its nodes. If there is a large commo

22、n mode voltage, the reference capacitor can gain charge (increase voltage) when called up to de-integrate a positive signal but lose charge (decrease voltage) when called up to de-integrate a negative input signal. This

23、differ</p><p>　　2.7 Analog COMMON</p><p>　　This pin is included primarily to set the common mode voltage for battery operation (ICL7106) or for any system where the input signals are floating wi

24、th respect to the power supply. The COMMON pin sets a voltage that is approximately 2.8V more negative than the positive supply. This is selected to give a minimum end-of-life battery voltage of about 6V. However, analog

25、 COMMON has some of the attributes of a reference voltage. When the total supply voltage is large enough to cause the zener to re</p><p>　　The limitations of the on chip reference should also be recognized,

26、however. With the ICL7107, the internal heating which results from the LED drivers can cause some degradation in performance. Due to their higher thermal resistance, plastic parts are poorer in this respect than ceramic.

27、 The combination of reference Temperature Coefficient (TC), internal chip dissipation, and package thermal resistance can increase noise near full scale from 25μV to 80μVP-P. Also the linearity in going from a hi</p&g

28、t;<p>　　The ICL7106, with its negligible dissipation, suffers from none of these problems. In either case, an external reference can easily be added, as shown in Figure 2.</p><p>　　Analog COMMON is al

29、so used as the input low return during auto-zero and de-integrate. If IN LO is different from analog COMMON, a common mode voltage exists in the system and is taken care of by the excellent CMRR of the converter. However

30、, in some applications IN LO will be set at a fixed known voltage (power supply common for instance). In this application, analog COMMON should be tied to the same point, thus removing the common mode voltage from the co

31、nverter. The same holds true for the refe</p><p>　　Within the lC, analog COMMON is tied to an N-Channel FET that can sink approximately 30mA of current to hold the voltage 2.8V below the positive supply (whe

32、n a load is trying to pull the common line positive). However, there is only 10μA of source current, so COMMON may easily be tied to a more negative voltage thus overriding the internal reference.</p><p>　　F

33、IGURE 2 USING AN EXTERNAL REFERENCE</p><p><b>　　2.8 TEST</b></p><p>　　The TEST pin serves two functions. On the ICL7106 it is coupled to the internally generated digital supply throu

34、gh a 500Ω resistor. Thus it can be used as the negative supply for externally generated segment drivers such as decimal points or any other presentation the user may want to include on the LCD display. Figures 3 and 4 sh

35、ow such an application. No more than a 1mA load should be applied.</p><p>　　The second function is a “l(fā)amp test”. When TEST is pulled high (to V+) all segments will be turned on and the display should read “

36、1888”. The TEST pin will sink about 15mA under these conditions.</p><p>　　FIGURE 3 SIMPLE INVERTER FOR FIXED DECIMAL POINT</p><p>　　FIGURE 4 EXCLUSIVE ‘OR’ GATE FOR DECIMAL POINT DRIVE</p>

37、<p>　　2.9 Digital Section</p><p>　　Figures 5 and 6 show the digital section for the ICL7106 and ICL7107, respectively. In the ICL7106, an internal digital ground is generated from a 6V Zener diode and

38、 a large P-Channel source follower. This supply is made stiff to absorb the relative large capacitive currents when the back plane (BP) voltage is switched. The BP frequency is the clock frequency divided by 800. For thr

39、ee readings/sec., this is a 60Hz square wave with a nominal amplitude of 5V. The segments are driven at the same fr</p><p>　　Figure 6 is the Digital Section of the ICL7107. It is identical to the ICL7106 exc

40、ept that the regulated supply and back plane drive have been eliminated and the segment drive has been increased from 2mA to 8mA, typical for instrument size common anode LED displays. Since the 1000 output (pin 19) must

41、 sink current from two LED segments, it has twice the drive capability or 16mA. </p><p>　　In both devices, the polarity indication is “on” for negative analog inputs. If IN LO and IN HI are reversed, this in

42、dication can be reversed also, if desired.</p><p>　　FIGURE 5 ICL7106 DIGITAL SECTION</p><p>　　FIGURE 6 ICL7107 DIGITAL SECTION</p><p>　　2.10 System Timing</p><p>　　Figu

43、re 7 shows the clocking arrangement used in the ICL7106 and ICL7107. Two basic clocking arrangements can be used:</p><p>　　1. Figure 7A. An external oscillator connected to pin 40.</p><p>　　2. F

44、igure 7B. An R-C oscillator using all three pins.</p><p>　　The oscillator frequency is divided by four before it clocks the decade counters. It is then further divided to form the three convert-cycle phases.

45、 These are signal integrate (1000 counts), reference de-integrate (0 to 2000 counts) and auto-zero (1000 to 3000 counts). For signals less than full scale, auto-zero gets the unused portion of reference de-integrate. Thi

46、s makes a complete measure cycle of 4,000 counts (16,000 clock pulses) independent of input voltage. For three readings/second, an o</p><p>　　To achieve maximum rejection of 60Hz pickup, the signal integrate

47、 cycle should be a multiple of 60Hz. Oscillator frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz, 40kHz, 33kHz, etc. should be selected. For 50Hz rejection, Oscillator frequencies of 200kHz, 100kHz, 66kHz, 50kHz, 40kHz

48、, etc. would be suitable. Note that 40kHz (2.5 readings/second) will reject both 50Hz and 60Hz (also 400Hz and 440Hz).</p><p>　　FIGURE 7 CLOCK CIRCUITS</p><p>　　三位半LCD/LED顯示A/D轉(zhuǎn)換器</p><

49、;p>　　摘要：ICL7106和ICL7107是高性能、低功耗的三位半A/D轉(zhuǎn)換電路。它包含有七段譯碼器、顯示驅(qū)動器、參考源和時鐘系統(tǒng)。ICL7106含有一背電極驅(qū)動線，適用于液晶顯示（LCD），ICL7107可直接驅(qū)動發(fā)光二極管（LED）。</p><p>　　ICL7106和ICL7107將高精度、通用性和真正的低成本很好地結(jié)合在一起，它有低于10μV的自動校零功能，零點漂移小于1Μv/℃，低于10pA

50、的輸入電流，極性轉(zhuǎn)換誤差小于一個計數(shù)。真正的差動輸入和差動參考源在各種系統(tǒng)中都很有用。在用于測量負(fù)載單元、壓力規(guī)管和其他橋式傳感器時會有更突出的優(yōu)點。另外，只要有十個左右的無源元件和一個LCD屏就可以與ICL7106構(gòu)成一個高性能的儀表面板，實現(xiàn)了低成本的單電源工作。</p><p>　　關(guān)鍵字：三位半 LCD/LED A/D轉(zhuǎn)換器</p><p><b>　　1 主

51、要特點</b></p><p>　　(1)保證零電平輸入時，各量程的讀值均為零。</p><p>　　(2)1pA典型輸入電流。</p><p>　　(3)真正的差動輸入和差動參考源，直接LCD顯示驅(qū)動（ICL7106）和LED顯示驅(qū)動（ICL7107）。</p><p>　　(4)很低的噪聲。（小于15μVp-p）。</p

52、><p><b>　　(5)芯片上時鐘。</b></p><p>　　(6)低功耗（典型值小于10mW）。</p><p>　　(7)不需外接有源電路。</p><p><b>　　2 詳細(xì)說明</b></p><p><b>　　2.1 模擬部分</b>&

53、lt;/p><p>　　圖1示ICL7106和ICL7107的模擬部分。每個測量周期分為三個階段，他們分別是（1）自動校零階段（A~Z）；（2）信號積分階段（INT）和（3）反向積分階段（DE）。</p><p>　　圖1 ICL7106和ICL7107的模擬部分</p><p>　　2.2 自動校零階段</p><p>　　在自動校零階段做三件

54、事。第一，內(nèi)部高端輸入和低端輸入與外部管腳脫開，在內(nèi)部與模擬公共管腳短接。第二，參考電容充電到參考電壓值。第三，圍繞整個系統(tǒng)形成一個閉合回路，對自動校零電容CAZ 進行充電，以補償緩沖放大器、積分器和比較器的失調(diào)電壓。由于比較器包含在回路中，因此自動校零的精度僅受限于系統(tǒng)噪聲。任何情況下，折合到輸入端的失調(diào)電壓小于10μV。</p><p>　　2.3 信號積分階段</p><p>　　在

55、信號積分階段，自動校零回路斷開，內(nèi)部短接點也脫開，內(nèi)部高端輸入和低端輸入與外部管腳相連。轉(zhuǎn)換器將IN HI和IN LO之間輸入的差動輸入電壓進行一固定時間的積分，此差動輸入電壓可以在一個很寬的共模范圍內(nèi)，與正、負(fù)電源的差距各為1V之內(nèi)。另一方面，若該輸入信號相對于轉(zhuǎn)換器的電源電壓沒有回轉(zhuǎn)，可將IN LO連接到模擬公共端上，以建立正確的共模電壓。在此積分階段的最后，積分信號的極性也已經(jīng)確定了。</p><p>　　

56、2.4 反向積分階段</p><p>　　最后一個積分階段是反向積分階段。低端輸入在芯片內(nèi)部連接到模擬公共端，高端輸入通過先前已充電的參考電容進行連接，內(nèi)部電路能使電容的極性正確地連接以確保積分器的輸出能回到零。積分器的輸出回到零的時間正比于輸入信號的大小。對應(yīng)的數(shù)字輸出為：顯示值=1000。</p><p><b>　　2.5 差動輸入</b></p>

57、<p>　　輸入端能承受輸入放大器允許的共模電壓范圍內(nèi)的差動電壓。即在比正電源低0.5V和比負(fù)電源高1V的范圍。在此范圍內(nèi)，電路有85dB的共模抑制比。然而必須注意的是積分器的輸出不能進入飽和區(qū)，一種最壞的情況可能是在輸入端有一接近滿量程的負(fù)向差動電壓，同時又有一個較大的共模正向電壓，負(fù)向的差動電壓使得積分器的輸出向正方向走，而此時積分器輸出的正向擺幅又被正向共模電壓所擠占，在這種嚴(yán)格的應(yīng)用條件下，可適當(dāng)?shù)貭奚恍┚龋瑢⒎e

58、分器的輸出電壓擺幅降低到低于所推薦的2V滿量程。積分器的輸出可在比正電源低0.3V或比負(fù)電源高0.3V的范圍內(nèi)擺動而不影響線性度。</p><p><b>　　2.6 差動參考源</b></p><p>　　參考電壓能夠在轉(zhuǎn)換器的電源電壓范圍內(nèi)的任意位置上產(chǎn)生。共模誤差的主要來源是翻轉(zhuǎn)電壓，這是由于參考電容對其接點上的分布電容充電或放電而造成的。如果有一較大的共模電壓

59、，在正電壓輸入下進行反向積分時，參考電容會得以充電（電壓增加）。反之，在負(fù)電壓輸入下進行反向積分時，參考電容會失去電荷。這種由于正負(fù)輸入電壓而在參考電容上造成的電壓差異會導(dǎo)致翻轉(zhuǎn)誤差。然而通過參考電容，使得它比分布電容大許多，則最壞情況下的誤差可以控制在0.5個顯示字之內(nèi)。</p><p><b>　　2.7 模擬公共端</b></p><p>　　此管腳主要是為在電

60、池供電的應(yīng)用場合（ICL7106）或輸入信號相對于供電電源是浮動的系統(tǒng)中建立一個公共電壓而設(shè)置的。COMMON管腳設(shè)置的電壓比正電源約低2.8V，這樣的選擇可以使電池電壓低至接近6V時仍能工作。然而，此模擬公共端有一些參考電壓的特征。只有當(dāng)總的供電電壓足夠高使得穩(wěn)壓管能工作時（>7V），此公共點的電壓才有較低的電壓系數(shù)（0.001%/V）和較低的輸入阻抗（≈15Ω），典型情況下的溫度系數(shù)小于80ppm/℃。</p>

61、<p>　　另外，片上參考源的一些不足也必須充分予以重視。在ICL7107中，由于驅(qū)動LED數(shù)碼管而導(dǎo)致的內(nèi)部發(fā)熱會使性能下降。由于塑料的熱阻比陶瓷的打，因此塑封電路比瓷封電路在這方面的性能要差，由于參考源的溫度系數(shù)、片上功耗和封裝的熱阻等原因，會使接近滿量程時的噪聲從25μVp-p上升到80μVp-p。另外，高功耗（例如顯示值為1000，二十段顯示）與低功耗（例如顯示值為1111，八段顯示）使得線性度之差會達到一個字，甚至更

62、多。參考源有正溫度系數(shù)的電路在量程溢出時會多出幾個字。這事因為溢出時三個低位數(shù)字均不顯示，而處于低功耗狀態(tài)。相似地，參考源為負(fù)溫度系數(shù)的電路會在溢出和非溢出讀值之間來回交替變化。這事由于芯片不斷被加熱和冷卻的結(jié)果。所以這些問題在使用外部參考源時自然就解決了。</p><p>　　ICL7106由于功耗很小，可以忽略，基本上就沒有上述這些問題。在兩種電路的應(yīng)用中，都可以方便地加上外故參考源，見圖2。</p&g

63、t;<p>　　模擬公共端在自動校零和反向積分期間與低端輸入回路相連。如果IN LO不同于模擬公共端，就會在系統(tǒng)中產(chǎn)生一共模電壓并會被電路優(yōu)異的共模抑制特性所抑制，然而在某些應(yīng)用場合，IN LO會被設(shè)置成一已知的固定電壓（比如電源的公共端），這樣，模擬公共端也應(yīng)該至此同一點，以消除電路上的共模電壓。此問題對于參考電壓也同樣重要。如果參考源能方便地接至模擬公共端，就必須要接。因為只有這樣才可以消除由于參考源系統(tǒng)而引入的共模電

64、壓。</p><p>　　在芯片內(nèi)部，模擬公共端連接至-N溝道場效應(yīng)管，該管子有約30mA的陷電流能力，以使模擬公共端的電壓維持在比電源電壓低2.8V（當(dāng)有一負(fù)載將此公共電網(wǎng)正上端拉時）。但是該模擬公共端只有10μA的源電流能力。由于此，COMMON端可方便地連接至負(fù)電壓而不必考慮內(nèi)部的參考源。</p><p>　　圖2 采用外部參考源的連接方法</p><p>&

65、lt;b>　　2.8 測試管腳</b></p><p>　　TEST管腳提供兩個功能。在ICL7106電路中，它通過—500Ω的電阻連接到內(nèi)部產(chǎn)生的數(shù)字部分電源。這樣，它提供外部產(chǎn)生的LCD字符端驅(qū)動電路的負(fù)電源。這些LCD驅(qū)動器可用來驅(qū)動顯示小數(shù)點或其他用戶希望在LCD屏上顯示的圖形或字符。圖3和圖4表示了這樣的應(yīng)用，注意這時所加的負(fù)載電流不能超過1mA。</p><p&g

66、t;　　第二個功能是“顯示測試”。當(dāng)TEST管腳置于高電平時（接V+），所有的LCD驅(qū)動端都顯示，顯示為“1888”，在這種方式下，TEST管腳可陷入大約15mA的電流。</p><p>　　圖3 為固定小數(shù)點顯示所采用的簡單反向器</p><p>　　圖4為多個小數(shù)點選擇顯示所采用的異或門電路</p><p><b>　　2.9 數(shù)字部分</b&g

67、t;</p><p>　　圖5和圖6分別畫出了ICL7106和ICL7107的數(shù)字部分框圖，在ICL7106中，有6V的穩(wěn)壓二極管和一個很大的P溝管子構(gòu)成的源極跟隨器形成了內(nèi)部數(shù)字的，這樣的電源連接方式在背極（BP）電壓以方波輸出時可吸納較大的容性電流。背極電壓的頻率為時鐘頻率除以800，在每次三秒讀數(shù)刷新速率時，它為60Hz的方波。標(biāo)稱電壓幅度為5V；LCD的端驅(qū)動電壓與此背極電壓同頻、同幅，不顯示時為同相，顯

68、示時為反相，在各種條件下，字符段兩端的平均直流電壓可以忽略。</p><p>　　圖6畫出了ICL7107的數(shù)字部分框圖。除了去掉穩(wěn)壓部分和背極驅(qū)動以及將字符驅(qū)動電流由2mA增加至8mA以滿足儀表上用的共陽LED數(shù)碼管的驅(qū)動要求之外，其余與ICL7106都是一樣的。由于千位的輸出（19引腳）要驅(qū)動兩個LED段，它的驅(qū)動能力加大一倍，達到16mA。</p><p>　　在這兩件器件中，有負(fù)電

69、壓輸入時，極性符號會被顯示（點亮）。必要時若低端輸入（IN LO）和高端輸入（IN HI）反接，則該指示也會反過來。</p><p>　　圖5 ICL7106數(shù)字部分框圖</p><p>　　圖6 ICL7107數(shù)字部分框圖</p><p><b>　　2.10 系統(tǒng)定時</b></p><p>　　圖7畫出了ICL71

70、06和ICL7107的時鐘連接方式，可在這兩種基本的連接方式中選擇一種使用。</p><p>　　（1）如圖7A中所示，一外接振蕩器連接到第40腳。</p><p>　?。?）如圖7B中所示，用三個管腳構(gòu)成R-C振蕩器。</p><p>　　該振蕩頻率被除以4，然后再進入下一級計數(shù)器，以形成一個測量周期的三個階段。它們是信號積分階段（1000個計數(shù)值），參考源反向積

71、分階段（0至2000個計數(shù)值）和自動校零階段（1000~3000個計數(shù)值）。在輸入信號小于滿量程時，自動校零將參考源中未用足的部分進行反積分，這樣，使得一個完整的測量過程為4000個計數(shù)值（16000個時鐘脈沖），而與輸入信號無關(guān)。需要每秒三次的讀數(shù)刷新速率時，可選用48KHz的振蕩頻率。</p><p>　　為使電路對60Hz的工頻有最大的抑制能力，信號積分階段的時間應(yīng)為60KHz的工頻的整數(shù)值，這樣，可選的振

72、蕩頻率為240kHz, 120kHz, 80kHz, 60kHz, 48kHz, 40kHz, 33kHz等，同樣的，為了對50KHz的工頻有最好的抑制能力，可選的振蕩頻率有200kHz, 100kHz, 66kHz, 50kHz, 40kHz等。請注意，40KHz的振蕩頻率（每秒2.5個讀數(shù)），對50KHz和60KHz的工頻均有抑制能力（400Hz和440Hz也可以）。</p><p><b>　　圖