外文翻譯--開發(fā)與plc功能和網(wǎng)絡等效的虛擬儀器

1、<p><b>　　英文原文</b></p><p>　　Journal of Software Engineering and Applications, 2011, 4, 172-180</p><p>　　doi:10.4236/jsea.2011.43019 Published Online March 2011 (http://www.SciRP.

2、org/journal/jsea)</p><p>　　Development of Equivalent Virtual Instruments to PLC Functions and Networks</p><p>　　Mohammad A. K. Alia, Tariq M. Younes, Mohammad Abu Zalata</p><p>　　Me

3、chatroncis Engineering Department, Faculty of Engineering Technology, Al-Balqa Applied University, Amman, Jordan.</p><p>　　Email: makalalia2000@yahoo.com, tariqmog@hotmail.com, abuzalata@yahoo.com</p>

4、<p>　　Received February 20th, 2011; revised March 5th, 2011; accepted March 10th, 2011.</p><p><b>　　ABSTRACT</b></p><p>　　This research is a continuation to our work which was

5、published in [1]. Eight different timing VIs are designed and tested. These include ON-Delay, OFF-Delay, Single Shot, Retriggerable Monostable, and Accumulative software-based timers. Using hardware programmable counter/

6、timer chip (DAQ-STC-24bit) and PCI MIO-16E-1 DAQ board, another two precise timers are designed. At the end of the paper, for illustration purposes, an electro-pneumatic drive system was developed and controlled utilizin

7、g desi</p><p>　　Keywords: PLC, Virtual PLC, LabVIEW, Programmable Timers</p><p>　　1. Introduction</p><p>　　In our work “Design of a virtual PLC using LabVIEW” we have shown how it i

8、s possible to create LabVIEW VIs which represent PLC functions and networks. We compared between PC-based and PLC-based control systems, and came to the fact that both systems are continuously developing in the same dire

9、ction in order to obtain better programmability, connectivity and communication interfacing. At the time being the PC-based DCSs are suited for industrial applications. They are robust and they easily work </p>&l

10、t;p>　　2. ON-Delay Timer</p><p>　　1) ON-Delay Timer-1</p><p>　　Figure 1 shows the front panel and the block diagram components of a software-based ON-Delay Timer. The loop iteration is indicat

11、ed in seconds. Because the loop iteration starts from zero, the increment function is added in order to start it at one. Since the wait icon has 100 ms delay between every two iterations a factor of 10 is multiplied by t

12、imer preassigned value, in order to measure the time delay in seconds. After the application of enable signal it takes some delay time interval for the</p><p>　　2) ON-Delay Timer-2</p><p>　　The

13、components of the VI are shown in the block diagram, Figure 2. Initially the input signal is not enabled and the false case is activated. The output of select icon will be zero, which is lower than the timer preset value

14、, and as a result of that the output of the timer is OFF. When the input signal is enabled the true case is executed and the select icon will output the value that comes form the output of the case structure. The initial

15、 value of the iteration local variable is zero, then it </p><p><b>　?。╝）</b></p><p><b>　　（b）</b></p><p><b>　　(c)</b></p><p>　　Figure

16、 1. On-delay timer-1, (a) The Block Diagram; (b) The Front Panel; (c) Subicon</p><p>　　3. OFF-Delay Time</p><p>　　1) OFF-Delay Timer-1</p><p>　　The front panel and block diagram are

17、 shown in Figure3. The while loop and other VI components are located inside the false case of the case structure. The true case has a local variable of the timer output, which is wired to the selector terminal. The enab

18、le input signal is connected to the selector terminal of the false case.</p><p>　　2) OFF-Delay Timer-2</p><p>　　The block diagram is given in Figure 4. When the input is enabled the true case is

19、 activated and the select icon will be selected to zero. In this case the output of the comparison function is false and the timer output is true. When the input signal is disabled the false case executes, and the select

20、 icon is selected to the value that comes from the output of the case structure. When the off-delay time interval elapses the output of the comparison function is true and the timer output is false.</p><p>&

21、lt;b>　　(a)</b></p><p><b>　　(b)</b></p><p>　　Figure 4. OFF delay timer 4, (a) True case; (b) False case</p><p>　　4. Single-Shot Timer</p><p>　　The b

22、lock diagram and front panel are shown in Figure 5. The Boolean indicator prevents the timer output to turn ON again after the elapse of the preset value of one-shot timer. During the false case the output is OFF, and du

23、ring the comparison time the timer output enabled high. At the end of comparison the timer output is low again.</p><p>　　5. Retriggerable Monostable Timer VI</p><p>　　Figure 6 shows the block di

24、agram and the front panel of this timer. When the enable input switches ON, the timer output immediately turns ON and the timer starts timing. As soon as the preset time value has elapsed, the timer output switches OFF,

25、even if the enable input is still ON. Every OFF to ON transition of the enable input resets the timer, i.e. the elapsed time is set to pre-set value and timer output is switched ON. Figure 7 shows a three mode delay time

26、r. ON delay, OFF delay and Retrig</p><p>　　6. Accumulative Timer–VI</p><p>　　The timer block diagram and front panel are shown in Figure 8. The output of the add function and the timer preset va

27、lue are connected to the equal comparison function. The output equal comparison function is connected to one terminal of the OR gate. The other input of the OR gate function is connected to the inverted input signal. The

28、 output of OR function is connected to conditional terminal of the while loop.</p><p><b>　　(a)</b></p><p><b>　　(b)</b></p><p><b>　　(c)</b></p&

29、gt;<p>　　Figure 3. OFF-delay timer, (a) The block diagram; (b) The front panel; (c) Subicon.</p><p>　　The conditional terminal is connected to one terminal of the AND gate. The other input of the AND

30、gate is connected to local variable of the input signal. The output of the AND gate is the timer output. The while loop and above mentioned components are inside the true case of the case structure. When the input signal

31、 is not enabled the false case is activated, then the local variable of accumulative indicator has a zero value and that value will be stored in the current time indicator. The true </p><p>　　7. Conclusions&

32、lt;/p><p>　　Using LabVIEW environment, seven different timing virtual instruments have been designed and tested. Applying the same approach it is possible to design a complete set of PLC functions in order to r

33、ealize able PC-based virtual PLC. In this case the virtual PLC will gain the advantages of PC-Based control.</p><p>　　REFERENCES</p><p>　　M. K. Abuzalata, M. A. Alia, et al., “Designing Virtual

34、PLC Using LabVIEW”, Applied Sciences Engineering and Technology, Maxwell Science Publication, UK, Vol.2, No. 3, 2010, p. 288.</p><p>　　“Function and VI Reference Manual,” National Instruments,1998 Edition, A

35、ustin, USA.</p><p>　　K. L. A. Shley, “Analog Electronics with LabVIEW,” Prentice Hall PTR, 2003.</p><p>　　T. Mohioddin and M. Nawroki, “LabVIEW Advance Programming Techniques,” Second Edition, C

36、RC Press, Boca Raton, 2006.</p><p>　　J. Essick, “Hands-on Introduction to LabVIEW for Scientists and Engineers,” Oxford University Press, USA,2008.</p><p>　　J. Y. Beyon, “Hands-on Exercise Manua

37、l for LabVIEW Programming, Data Acquisition and Analysis,” Prentice Hall PTR, USA, 2003.</p><p>　　B. E. Paton, “Sensors, Transducers and LabVIEW,” Prentice Hall International (UK) Limited, London, 1993.</

38、p><p><b>　　中文譯文</b></p><p>　　軟件工程與應用,學報2011,4,172 - 180 </p><p>　　開發(fā)與PLC功能和網(wǎng)絡等效的虛擬儀器</p><p>　　Mohammad A. K. Alia, Tariq M. Younes, Mohammad Abu Zalata</p&g

39、t;<p>　　Received February 20th, 2011; revised March 5th, 2011; accepted March 10th, 2011.</p><p><b>　　摘要</b></p><p>　　本研究是對我們工作的一個延續(xù),發(fā)表在[1]。設計和測試了八個不同的時間VIs。這包括延遲打開、延遲斷開、單發(fā)射擊、

40、可在觸發(fā)的單穩(wěn)態(tài)、累計計時器軟件。使用硬件可編程計數(shù)器/定時器芯片設計(DAQ-STC-24bit)和PCI MIO-16E-1 DAQ板兩個精確的計時器。在本文的結尾，開發(fā)一個電動氣動驅動系統(tǒng)和利用對延遲計時器控制設計VI功能，來解釋。實驗結果顯示基于plc程序控制和基于plc虛擬兩者之間的結果是一致的。</p><p>　　關鍵詞：可編程控制器，PLC虛擬，虛擬儀器，可編程定時器</p><

41、;p><b>　　介紹</b></p><p>　　我們的工作“使用虛擬儀器設計虛擬PLC”，我們已經(jīng)表明我們可以創(chuàng)建代表的PLC功能和網(wǎng)絡的虛擬儀器?！∥覀儽容^基于PC和基于PLC的控制系統(tǒng),來得到兩個系統(tǒng)不斷在同一方向發(fā)展以取得更好的可編程性、連通性和連通接口。同時基于PC的DCSs是適合工業(yè)應用的。他們是健大的和他們輕松地工作在一個開放的架構模式,雖然PLC是配備特定的MMI軟件

42、和偽標準變換軟件。我們表明,為了提高的可編程性PACs,我們幾乎把計算機的眾多優(yōu)點的PLC作為多任務,無限的記憶,高速和可能創(chuàng)造出無限數(shù)量的可編程對象如計數(shù)器、計時器、移位寄存器和其他。因為之前的工作規(guī)模有限,我們不能覆蓋其他重要的工作，使用和模擬PLC功能。本文我們開發(fā)不同類型的使用虛擬儀器軟件[2]和NI DAQ板硬件的可編程定時器。虛擬儀器的基本功能,提供時間在毫秒級的“等待”和“等待多個“VIs。兩者都是基于相同的底層機制。大多

43、數(shù)應用程序工作的舒適,可用虛擬儀器測量,解決毫秒,更多的操作與第二分辨率[3 - 4]。一些應用程序的需求和響應時間毫秒級的決議,這是有問題的,主要是由于操作系統(tǒng),而不是一個虛擬儀器限制[5]。一些應用程序的需求和響應時間毫</p><p><b>　　2、 接通延時時間</b></p><p><b>　　1）、接通延時-1</b></p

44、><p>　　圖1顯示了前面板和程序框圖的組件軟件在延遲計時器。循環(huán)迭代顯示秒。由于循環(huán)迭代開始從零,增加功能被添加以啟動它在一個。因為等待圖標有100毫秒的延遲每兩個迭代之間的10倍乘以定時器預先指定的值,為了測量時間延遲在秒。應用程序的啟動信號后,它需要一些延遲時間間隔相等的功能有一個真正的狀態(tài)輸出。如果輸入信號是禁用的,定時器輸出立即改變低狀態(tài)。</p><p><b>　　2

45、）接通延時-2</b></p><p>　　VI的組件顯示在框圖2。最初輸入信號不啟用和虛假的情況下被激活。選擇圖標的輸出是0,即低于預設值,定時器的結果是輸出的計時器是關閉的。當輸入信號是使真正的案件執(zhí)行,選擇圖標將輸出值,來自輸出案例的結構。迭代初始值的局部變量是零,那么它將增加所造成的延遲后等待圖標,然后由定時器預設值相比。當比較函數(shù)的輸出是正確的,輸出的定時器就高。當允許輸入信號就低,輸出的計

46、時器同時就低。在這個VI,檢查案例的結構是連續(xù)在一個掃描速率等于一毫秒,接受許多應用程序。</p><p><b>　?。╝）</b></p><p><b>　　（b）</b></p><p><b>　?。?）</b></p><p>　　在延遲定時器,(a)框圖;(b)面

47、板(c)功能</p><p><b>　　3、關閉延時</b></p><p><b>　　1）關閉延時-1</b></p><p>　　前面板和方塊圖是圖3所示。當循環(huán)和其他VI組件的位置在錯誤的情況下的情況下結構。真實的案例有一個局部變量定時器的輸出,這是連接到選擇器終端。允許輸入的信號連接到選擇器終端的虛假情況。&l

48、t;/p><p><b>　　2）關閉延時-2</b></p><p>　　給出了框圖如圖4。當輸入是啟用的情況下被激活的真實和選擇圖標將被選定為零。在這種情況下,輸出的比較函數(shù)是假和定時器輸出是正確的。當輸入信號是禁用的虛假案件執(zhí)行,選擇圖標被選中的值來自輸出案例的結構。當關閉延遲時間間隔過后比較函數(shù)的輸出是真的和定時器輸出是假的。</p><p&g

49、t;<b>　?。╝）</b></p><p><b>　?。╞）</b></p><p><b>　　(a)真（b）假</b></p><p><b>　　4、單發(fā)定時器</b></p><p>　　和前面板的框圖如圖5所示。布爾指示器防止定時器輸出后再

50、打開的推移預設值一次性計時器。在錯誤的情況下,輸出是關閉的,在比較時間定時器輸出使高。最后比較計時器再次低輸出。</p><p>　　5、可再觸發(fā)的單穩(wěn)態(tài)定時器VI</p><p>　　圖6顯示了框圖和前面板的計時器。當允許輸入開關,定時器輸出立即打開,計時器開始計時。一旦預定時間價值已經(jīng)運行,定時器輸出開關關閉,即使允許輸入仍在。每一個去在過渡的允許輸入重置計時器,即運行時間設置為預設值

51、,定時器輸出接通。圖7顯示了一個三模延遲計時器。在延遲,延遲斷開和可再觸發(fā)的單穩(wěn)態(tài)計時器是建立在一個框圖,程序員可以選擇所需的定時器模式。</p><p><b>　　6、累計計時器vi</b></p><p>　　計時器框圖和前面板如圖8所示。添加函數(shù)的輸出和計時器預設值是連接到平等的比較函數(shù)。輸出相等的比較函數(shù)連接到一個終端的或門。的另一個輸入或門函數(shù)連接到反向輸

52、入信號?；蚝瘮?shù)的輸出終端連接到有條件的while循環(huán)。</p><p><b>　　（a）</b></p><p><b>　?。╞）</b></p><p><b>　　(c)</b></p><p>　　(a)框圖;(b)前面板;(c)功能</p><p

53、>　　有條件的終端連接到一個終端的和門。其他輸入的與門連接到本地變量的輸入信號。與門的輸出是定時器輸出。while循環(huán)和上述組件是在真實情況下案例的結構。當輸入信號是不啟用虛假情況下被激活,那么局部變量的累積指標有一個零值,這個值將被存儲在當前時間指示器。真實的情況下將啟動時的輸入信號是啟用的。如果輸入信號是殘疾人平等比較函數(shù)之前是正確的,錯誤的情況下被激活和本地變量的循環(huán)迭代有價值的循環(huán)停止,這個值將被存儲在當前時間指示器。如果

54、輸入信號被再次激活,真正的情況下被激活和前面的操作再次重復,循環(huán)迭代添加到之前的值,這是存儲在當前的定時器起訴者,那么它就是與計時器預設值。流程的建立及顯示輸入信號持續(xù)進行直到輸出相等的比較函數(shù),結果變成真正的定時器輸出打開。硬件可編程計數(shù)器/定時器芯片(DAQSTC-24鉆頭)和硬件時基信號來源位于PCI-MIO-16E-1板是利用。該計劃是建立采用先進subVIs因為他們更靈活的比容易VIs或中間vi。一個密切相關的問題是使用兩個硬

55、件計數(shù)器測量的采樣時間間隔。在這種情況下信號的興趣喂養(yǎng)計數(shù)器源終端和終端的另一個計數(shù)器。源終端的第二個計數(shù)器是美聯(lián)儲通過定期時鐘信號</p><p><b>　　7、結論</b></p><p>　　使用虛擬儀器環(huán)境,七種不同的定時虛擬儀器設計和測試。運用同樣的方法可以設計一套完整的PLC功能以實現(xiàn)能夠基于pc的虛擬PLC。在這種情況下,虛擬PLC將獲得的優(yōu)勢,基于p

56、c的控制。</p><p><b>　　參考文獻</b></p><p>　　M. K. Abuzalata, M. A. Alia, et al., “Designing Virtual PLC Using LabVIEW”, Applied Sciences Engineering and Technology, Maxwell Science Publicati

57、on, UK, Vol.2, No. 3, 2010, p. 288.</p><p>　　“Function and VI Reference Manual,” National Instruments,1998 Edition, Austin, USA.</p><p>　　K. L. A. Shley, “Analog Electronics with LabVIEW,” Prent

58、ice Hall PTR, 2003.</p><p>　　T. Mohioddin and M. Nawroki, “LabVIEW Advance Programming Techniques,” Second Edition, CRC Press, Boca Raton, 2006.</p><p>　　J. Essick, “Hands-on Introduction to Lab

59、VIEW for Scientists and Engineers,” Oxford University Press, USA,2008.</p><p>　　J. Y. Beyon, “Hands-on Exercise Manual for LabVIEW Programming, Data Acquisition and Analysis,” Prentice Hall PTR, USA, 2003.&l