外文翻譯--用spmc75的pdc定時(shí)器做bldc電機(jī)的速度檢測(cè)

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1、　　BLDC Motor Speed Estimation Using PDC Timer Module　　1 Speed Calculation of BLDC 　　1.1 Summary of BLDC　　Since current BLDC has substituted the elec

2、trical commutator for the mechanical one, it eliminates the disadvantages of noise, spark, electromagnetic disturbance, short lifetime, etc. Now BLDC is provided with advantages of simple structure, dependable operation

3、and easy maintenance as AC motor does, as well as advantages of high efficient, no excitation cost and functional speed regulation as traditional DC motor does. So it is widely used in various fields of industrial contro

4、l now.　　1.2 PDC Module Introduction 　　SPMC75F2413A provides two channels of 16 bit PDC (Phase Detection Control, PDC) timers used for capture function and PWM operation. It also

5、supports position detection features for Brushless-DC motor application. The PDC timers are very suitable for both mechanical speed calculation, with ACI and BLDC motor included, and phase commutation for changing curren

6、t conduction according to position information. Figure 1-1 shows the block diagram of entire PDC timers, channel 0 and channel 1. For detail　　Table 1-1 PDC Timer　　Figure 1-1 PDC

7、Timers Block Diagram 　　1.3 PDC Operation 　　This note mainly depicts PDC application in motor speed measurement. For detailed PDC introduction, please refer to “SPMC75F2413A Progr

8、amming Guide” authored by Sunplus. 　　PDC module has four types of registers to perform speed measurement: Timer control register P_TMRx_Ctrl (x = 0, 1), position detection control register P_POSx_Dec

9、tCtrl (x = 0, 1), input output control register P_TMRx_IOCtrl (x = 0, 1), and timer interrupt enable register P_TMRx_INT (x = 0, 1). Where, P_TMRx_Ctrl and P_POSx_DectCtrl are introduced in detail.

10、　1.31Input Output Control Register 　　P_TMRx_Ctrl(x = 0, 1)　　Bit 15:14 　　SPCK: Capture input sample clock select. These bits select the capture input sample c

11、lock. Capture input will be sampled with sample clock. Pulses shorter than four sample clocks will be considered invalid, and will be ignored.　　00 = FCK/1 　　01 = FCK/2

12、　　10 = FCK/4 　　11 = FCK/8　　Bit 13:10 　　MODE: Modes select. These bits are used to select the timer operation modes. 　　0000 = N

13、ormal operation (continuous counter up counting) 　　0100 = Phase counting mode 1 　　0101 = Phase counting mode 2 　　0110 = Phase counting mode 3 <

14、;p>　　0111 = Phase counting mode 4 　　1x0x = Edge-aligned PWM mode (continuous counter up counting, PWM output) 　　1x1x = Center-aligned PWM mode (continuous counter up/down coun

15、ting, PWM output)　　Bit 9:8 　　CLEGS: Counter clear edge select. These bits select the counter clearing edge when the clearing source is in input capture mode.&l

16、t;/p>　　00 = do not clear 　　01 = rising edge 　　10 = falling edge 　　11 = both edge　　Bit 7:5 &

17、lt;p>　　CCLS: Counter clear source select. These bits select the TCNT counter clearing source. 　　000 = TCNT clearing disabled 　　001 = TCNT cleared by P_TMRx_TGRA (x = 0, 1) cap

18、ture input 　　010 = TCNT cleared by P_TMRx_TGRB (x = 0, 1) capture input 　　011 = TCNT cleared by P_TMRx_TGRC (x = 0, 1) capture input 　　100 = TCNT cleared by

19、every P_POSx_DectData (x = 0, 1) change 6 times　　101 = TCNT cleared by every P_POSx_DectData (x = 0, 1) change 3 times 　　110 = TCNT cleared by P_POSx_DectData (x = 0, 1) position

20、 detection data change 　　111 = TCNT cleared by P_TMRx_TPR (x = 0, 1) compare match　　Bit 4:3 　　CKEGS: Clock edge select, These bits select

21、 the input clock edge. When the input clock is counted using both edges, the input clock period is halved. When FCK/1 is selected as counter clock, counter will count at rising edge if count at both edges is selected.<

22、;/p>　　00 = Count at rising edge 　　01 = Count at falling edge 　　1X = Count at both edges　　Bit 2:0 　　TMRPS: Timer pre-sca

23、lar select. These bits select the TCNT counter clock source. It can be selected independently for each channel.　　000 = Counts on FCK /1 　　001 = Counts on FCK /4 <p

24、>　　010 = Counts on FCK /16 　　011 = Counts on FCK /64 　　100 = Counts on FCK /256 　　101 = Counts on FCK /1024 　　110 = Counts on TCLKA p

25、in input 　　111 = Counts on TCLKB pin input　　Control register configuration 　　P_TMRx_Ctrl(x = 0, 1) is used for the selection of input capture during speed me

26、asurement. Rather than being a general input signal, the input capture is a period between two position detection changes triggered by PDC interrupt. This period must be counted with a certain frequency supported by a cl

27、ock source. Thus, the counters on this function must be configured. 　　MODE: Select a timer operation mode in seven modes. However, only the normal operation (continuous counter up counting) mode can

28、be selected in this application, because the other six modes are all related to phase counting mode or PWM mode. 　　CCLS: Select a TCNT counter clearing source from eight settings. In this application

29、, one among the three can be set: 100, 101 or 110, which respectively indicates that TCNT is cleared for once every 6/3/1 times P_the POSx_DectData (x = 0, 1) changes. Also, they can be described as: TCNT is cleared for

30、once every 360/180/60 electrical degree rotation of BLDC. This setting is critical for converting electrical revolution to mechanical revolution and measuring the BLDC speed.　　CKEGS: Select the input

31、 clock edge, which can be rising, falling or both edges. When the input clock is counted using both edges, the input clock period is halved. Note to count this factor on during the BLDC speed calculation. <

32、;p>　　TMRPS: Select the TCNT counter clock source from eight settings. This setting determines the precision and the range during BLDC speed measurement. See the example code below: 　　P_TMR0_Ctrl,

33、B.MODE = 0; // Normal Counting mode 　　P_TMR0_Ctrl, B.CCLS = 6; // TCNT cleared by P_POSx_DectData (x = 0, 1) 　　// Each time position detection data ch

34、ange 　　P_TMR0_Ctrl, B.CKEGS = 0; // Counting at rising edge 　　P_TMR0_Ctrl, B.TMRPS = 3; // Select FCK/64 clock source <p&g

35、t;　　1.3.2 Position Detection Control Register 　　P_POSx_DectCtrl(x = 0, 1) 　　Bit 15:14 　　SPLCK: Sampling clock select. Select FCK/4, FCK/8, FCK/32, or FCK/1

36、28 for position sampling clock 　　00 = FCK/4 　　01 = FCK/8 　　10 = FCK/32 　　11 = FCK/128　　Bit 13:12

37、　　SPLMOD: Sampling mode select. Select one of three modes: sampling when PWM signal is active (PWM is on), sampling regularly, or sampling when lower side (UN, VN, WN) phases are conducting current.

38、　　00 = Sample when UPWM/VPWM/WPWM bit is set in P_TMRx_OutputCtrl (x = 3, 4) register and generate the PWM waveform　　01 = Sample regularly 　　10 = Sample when

39、 lower phases is in active state and conducting current 　　11 = Reserved　　Bit 11:8　　SPLCNT: Sampling count select. These bits select the sa

40、mpling count for the valid external position detection signals. The position signals must be sampled continuously match as many times as the sampling count set, for the position signals to be considered valid. The valid

41、settings are from 1 to 15 times. Note that count 0 and 1 are assumed to be one time.　　Bit : 7　　PDEN: Position detection enable. This bit enables/disables the p

42、osition detection function for position input pins TIOA~C. When enabled, the input signals of these pins will be sampled and the results will be latched to PDR [2:0] bits in POS_DectData register. When disabled, PDR [2:0

43、] will remain its status. 　　0 = Disable 　　1 = Enable　　Bit 6:0　　SPDLY: Sampling delay. These bits set a delay time clo

44、ck in which at SPLCK clock source. It is used to stop sampling in order to prevent erroneous detection due to noise that occurs immediately after PWM output turns on.　　Position detection control regi

45、ster 　　When the position detection changing event occurs, the P_TMRx_TCNT (x = 0, 1) value can be transferred to TGRA. If the position detection interrupt enable bit PDCIE is set to 1 in the correspo

46、nding P_TMRx_INT (x = 0, 1) register, the PDC interrupt routine will be called to process the data. 　　SPLCK: Select sampling clock from FCK/4, FCK/8, FCK/32, or FCK/128 for position sampling clock, w

47、hich determines the detection precision of position change. Proper setting of SPLCK, SPLCNT and SPDLY will help to prevent erroneous detection and filter the disturbance. 　　SPLMOD: Select one of thes

48、e three modes: sampling when PWM signal is active (PWM is on), sampling regularly, or sampling when lower side (UN, VN, WN) phases are conducting current. 　　SPLCNT: Sampling count select. The valid s

49、ettings are from 1 to 15 times. Note that count 0 and 1 are both assumed to be one time. 　　PDEN: This bit enables/disables the position detection function for position input pins TIOA~C.

50、　　SPDLY: Sampling delay with the range of 0 to 127.　　The setting example is shown as blew. 　　P_POS0_DectCtrl, B.SPLCK = 2; // Count on FCK/32 </p

51、>　　P_POS0_DectCtrl, B.SPLMOD = 1; // Sample regularly 　　P_POS0_DectCtrl, B.SPLCNT = 10; // Sample 10 times 　　P_POS0_DectCtrl,

52、B.PDEN = 1; // Enable position detection　　P_POS0_DectCtrl, B.SPDLY = 100; // Sample Delay　　1.4 Speed Calculation　　In ord

53、er to obtain the exact parameters, the data must be filtered after captured. There are many filter algorithms, such as low-pass filter, moving average filter, median filter, average filter, limiting filtering, first-orde

54、r filter, moving average filtering, etc. In general, the data can be considered valid after processed by these filters. Then the speed can be calculated by substituting these parameters data in the formula. &

55、lt;p>　　Assume Fcap is PDC capture clock frequency; p is the pole-pair of BLDC rotor; TCNT is cleared every m P_POSx_DectData (x = 0, 1) changes, that is, TCNT is cleared at every rad rotation (m=1, 3, 6), and the posi

56、tion data is Ncap　　Since: (Formula 1- 1)　　and =, 　　Since electrical degree = p x mechanical ro

57、tation then the mechanical angular 　　velocity is (Formula 1- 2)　　with the unit of rad/min. Take n as the indicator.

58、　　So: rad/min (Formula 1- 3) 　　n summarize: rpm (Formula 1- 4) 　　From the formula above, we can obverse that n is related to Fcap, m,

59、 Ncap and p (that is a constant when BLDC is selected) .　　Suppose there is a BLDC with 2 pole-pair, 4000rpm rated speed. We will show you how to set the parameters of Fcap and m.

60、;　　When m= 1, TCNT is cleared every time P_POSx_DectData (x = 0, 1) changes, , that is, TCNT is cleared for once every 60 electrical degree rotation of BLDC. 　　With a certain clock frequency, the mot

61、or rotation speed can be calculated by the Formula 1- 4 at the highest speed when Ncap is 1 and the lowest speed when Ncap is 0xffff. 　　Table 1-2 Motor Speed VS Clock Frequency

62、＠When m= 3, TCNT is cleared for once every 3 times P_POSx_DectData (x = 0, 1) changes, that is, TCNT is cleared every 180 electrical degree rotation of BLDC. 　　From the Formula 1- 4, we can see that

63、the measurable motor speed when m= 3 is three times higher than that when m= 1, provided that other parameters are the same. 　?。繵hen m= 6, TCNT is cleared every 6 times P_POSx_DectData (x = 0, 1) cha

64、nges, that is, TCNT is cleared every 360 electrical degree rotation of BLDC.　　From the Formula 1- 4, we can see that the measurable motor speed when m= 6 is six times higher than that when m= 1, prov

65、ides that other parameters are the same. 　　Above all, it is better to set m= 1 to ensure the veracity of positions. Since the highest speed can be applied, it is important to select the lowest speed.

66、 Assume the lowest measure speed is 200 rpm, we can set Fcap as FCK/16, FCK/64, FCK/256 or FCK/1024. FCK/16 is recommended to be selected for higher veracity.　　1.5 Noise Immunity

67、;　　Through programming the bit value of SPLCNT (sampling count select) and SPDLY (sampling delay) in P_POSx_DectCtrl(x = 0, 1), users could avoid the erroneous detection due to noise that occurs immediately after PWM out

68、put turns on. It can ensure the correctness of speed measurement and phase commutation in BLDC . 　　The valid settings are from 1 to 15 times. Note that count 0 and 1 are both assumed to be one time.

69、These bits select the sampling count for the valid external position detection signals. The position signals must be sampled continuously match as many times as the sampling count set, for the position signals to be cons

70、idered valid. Then the sharp pulse can be filtered by this method. SPLCK selects the sampling clock. Figure 1-2 shows the sampling counting and Figure 1-3 shows the noise immunity 　　Figure 1-2 Sampli

71、ng Counting 　　Figure 1-3 Noise Immunity Pulse 　　See Figure 1-2 , the SPLCNT setting is 10. When sampling the position signal with the frequency that SPLCK selected, a high-to-low

72、 transition occurs in hall3 at 0 to1 counting. Then sample the hall signal for ten executive times. If they are all of the same value, the hall signal can be considered valid. 　　When SPLCNT setting i

73、s 10, a high-to-low transition occurs in hall3 at the first counting, while a low-to-high transition occurs at the fourth counting. Then reset the counter, sample hall3 for ten executive times. If they are all of the sam

74、e value, the position signals can be considered as 011b still. By this way, a sharp pulse occurring in the signals can be filtered, which prevents the position signals from being disturbed. So the position signal will no

75、t be sampled if it varies quicker than 　　2 Software Design 　　2.1 Software Description 　　This application note is designed for motor speed measurement when dr

76、iving BLDC, which is performed by PDC position detection change interrupt. 　　2.2 Source File 　　2.3 DMC Interface　　Speed1_Now: Current speed by calculation &l

77、t;/p>　　User_R0: PDC Data captured by PDC interrupt 　　2.4 Subroutines 　　3 Design Tips 　　3.1 Demo Listing 　　/*= = = = = =

78、= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = */ 　　// Example 　　/*= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = */ </p&

79、gt;　　#include "Spmc75_regs.h" 　　#include "Spmc_typedef.h" 　　#include "unspmacro.h" 　　#include "Spmc75_SPDET.h&q

80、uot; 　　main() 　　{ 　　Spmc75_System_Init(); //System initialization 　　while(1) &l

81、t;/p>　　{ 　　MC75_DMC_UART_Service(); //DMC service 　　} 　　} 　　//= =

82、 = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =　　// Description: IRQ1 interrupt source is XXX, used to XXX 　　// Notes: Speed measurement through

83、PDC 　　//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 　　void IRQ1(void)__attribute__((ISR)); 　　void IRQ1(void) </p

84、>　　{ 　　if(P_TMR0_Status, B.PDCIF && P_TMR0_INT, B.PDCIE) 　　{ 　　Spmc75_PDCETSPD_ISR(); // PDC capt

85、ure interrupt for the motor speed calculation. 　　} 　　} 　　//= = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

86、= = = = = = = = = = = = 　　// Description: IRQ6 interrupt source is XXX, used to XXX 　　// Notes: DMC receiving ISR 　　//= = = = = = = = = = = = = = = = = = = =

87、 = = = = = = = = = = = = = = = = = = = = = = 　　void IRQ6(void) __attribute__ ((ISR)); 　　void IRQ6(void) 　　{ 　　if(P_IN

88、T_Status, B.UARTIF) 　　{ 　　if(P_UART_Status, B.RXIF) MC75_DMC_RcvStream(); 　　} 　　} </b&

89、gt;　　Sub-function for speed measurement 　　#define TMRPSFCK (24.0E+6)/64 //Counter clock source 　　#define PAIRPOLE 2 //BLDC pole pairs

90、#define PDCCLEAR 1 //CNT clear source 　　#define SPDLIMIT 5000 //Define the highest motor speed to avoid the disturbance due to sharp pulse 　　#define RADIX (UInt32)((TMRPSFCK*60*P

91、DCCLEAR) //(6*PAIRPOLE)) 　　#define MAXRPM (UInt16)(RADIX/SPDLIMIT) 　　static UInt16 a Filter[CAPBSIZE]; //Moving average filter data 　　static UInt16 *ptr = a

92、Filter; //Pointer to array 　　void Spmc75_PDCETSPD_ISR(void) 　　{ 　　static UInt32 summation= 0; 　　UInt16 original, uiSp

93、eed; 　　P_TMR0_Status, B.PDCIF = 1; // Clear interrupt flag 　　original = P_TMR0_TGRA, W; //Read PDC captured data 　　//Limit th

94、e highest speed 　　if(original > P_TMR0_TCNT, W && original > MAXRPM) 　　{ 　　//Accumulate the captured data and perform moving

95、 filter 　　summation -= *ptr; 　　*ptr = original; 　　summation += *ptr; 　　//Loop the array 　　if((++ptr) > (a Filter

96、+CAPBSIZE-1)) ptr = a Filter;　　// Average the accumulation data 　　original = (UInt16)(summation >> SHIFTDIV); 　　uiSpeed = (UInt32)RADIX/original; </

97、p>　　//Speed calculation 　　SPMC_DMC_Save_Aux(0, original); 　　//Transmit captured data to DMC 　　SPMC_DMC_Save_SpdNow(1, uiSpeed); <

98、;p>　　//Send data to DMC 　　} 　　} 　　3.2 Main Process Description 　　The main program performs syst

99、em initialization and DMC data detection. While the DMC data detection can also be performed in a timer interrupt with a certain frequency. Figure 3-1 shows the coding flow. 　　Figure 3-1 Main Process

100、 　　3.3 ISR Description　　In PDC interrupt, system reads and filters the data, then calculates the motor speed. The coding flow is shown as Figure 3-2 . 　　Figu

101、re 3-2 ISR Process 　　3.4Testing Hardware 　　This example is designed for the purpose of study and reference, so we simply need to input a position signal to test the system. The h

102、ardware connection is shown as Figure 3-3 . 　　Figure 3-3 Test Hardware Connection 　　Where, the position signal can be generated by MCU or special timing logic circuit instead of

103、necessarily being the real signal from BLDC (see Figure 3-4 and Figure 3-5 ). The frequency of position detection change can be adjusted by the potentiometer or ADC in MCU system 　　Figure 3-4 Hall Si

104、gnal 　　Figure 3-4 shows the three position signals timing with the sequence of 010b, 011b, 001b, 101b, 100b, 110b. 　　Figure 3-5 Hall signal 　　Figure 3-5 show

105、s Hall3, Hall2, Hall1 timing with the sequence of 110b, 100b, 101b, 001b, 011b, 010b. It is the same to test in real BLDC. The two timings present the different motor directions: move forward or move backward.

106、　　The Hall.spj file in Appendix shows the code for simulating hall signal with SPMC75F2413A. We can use ADC0 voltage to simulate the speed variation, where IOD15, IOD14 and IOD13 are corresponding to Hall3, Ha

107、ll2 and Hall1 respectively and IOA0/AN0 is used for ADC conversion to adjust the simulated speed. 　　用SPMC75的PDC定時(shí)器做BLDC電機(jī)的速度檢測(cè)　　一、BLDC的速度測(cè)算　　1 直流無刷電動(dòng)機(jī)概述</

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外文翻譯--用spmc75的pdc定時(shí)器做bldc電機(jī)的速度檢測(cè)

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