電氣控制工程外文翻譯

1、<p><b>　　附錄</b></p><p><b>　　附錄1 外文文獻</b></p><p>　　C8051F020 （PORT INPUT/OUTPUT）</p><p>　　The C8051F020/1/2/3 are fully integrated mixed-signal System o

2、n a Chip MCUs with 64 digital I/O pins (C8051F020/2) or 32 digital I/O pins (C8051F021/3), organized as 8-bit Ports. The lower ports: P0, P1, P2, and P3, are both bit- and byte-addressable through their corresponding Por

3、t Data registers. The upper ports: P4, P5, P6, and P7 are byte-addressable. All Port pins are 5 V-tolerant, and all support configurable Open-Drain or Push-Pull output modes and weak pull-ups. </p><p>　　The

4、C8051F020/1/2/3 devices have a wide array of digital resources which are available through the four lower I/O Ports: P0, P1, P2, and P3. Each of the pins on P0, P1, P2, and P3, can be defined as a General-Purpose I/O (GP

5、IO) pin or can be controlled by a digital peripheral or function (like UART0 or /INT1 for example), as shown in Figure 17.2. The system designer controls which digital functions are assigned pins, limited only by the num

6、ber of pins available. This resource assignment flexibil</p><p>　　The Priority Crossbar Decoder, or “Crossbar”, allocates and assigns Port pins on Port 0 through Port 3 to the digital peripherals (UARTs, SMB

7、us, PCA, Timers, etc.) on the device using a priority order. The Port pins are allocated in order starting with P0.0 and continue through P3.7 if necessary. The digital peripherals are assigned Port pins in a priority o

8、rder which is listed in Figure 17.3, with UART0 having the highest priority and CNVSTR having the lowest priority.</p><p>　　The Crossbar assigns Port pins to a peripheral if the corresponding enable bits of

9、the peripheral are set to a logic 1 in the Crossbar configuration registers XBR0, XBR1, and XBR2, shown in Figure 17.7, Figure 17.8, and Figure 17.9. For example, if the UART0EN bit (XBR0.2) is set to a logic 1, the TX0

10、and RX0 pins will be mapped to P0.0 and P0.1 respectively. Because UART0 has the highest priority, its pins will always be mapped to P0.0 and P0.1 when UART0EN is set to a logic 1. If a digital per</p><p>　　

11、All Port pins on Ports 0 through 3 that are not allocated by the Crossbar can be accessed as General-Purpose I/O (GPIO) pins by reading and writing the associated Port Data registers ，a set of SFRs which are both byte- a

12、nd bit-addressable. The output states of Port pins that are allocated by the Crossbar are controlled by the digital peripheral that is mapped to those pins. Writes to the Port Data registers (or associated Port bits) wil

13、l have no effect on the states of these pins.</p><p>　　A Read of a Port Data register (or Port bit) will always return the logic state present at the pin itself, regardless of whether the Crossbar has alloca

14、ted the pin for peripheral use or not. An exception to this occurs during the execution of a read-modify-write instruction (ANL, ORL, XRL, CPL, INC, DEC, DJNZ, JBC, CLR, SET, and the bitwise MOV operation). During the re

15、ad cycle of the read-modify-write instruction, it is the contents of the Port Data register, not the state of the Port pins them</p><p>　　Because the Crossbar registers affect the pinout of the peripherals o

16、f the device, they are typically configured in the initialization code of the system before the peripherals themselves are configured. Once configured, the Crossbar registers are typically left alone.</p><p&g

17、t;　　Once the Crossbar registers have been properly configured, the Crossbar is enabled by setting XBARE (XBR2.6) to a logic 1. Until XBARE is set to a logic 1, the output drivers on Ports 0 through 3 are explicitly disab

18、led in order to prevent possible contention on the Port pins while the Crossbar registers and other registers which can affect the device pinout are being written.</p><p>　　The output drivers on Crossbar-ass

19、igned input signals (like RX0, for example) are explicitly disabled; thus the values of the Port Data registers and the PnMDOUT registers have no effect on the states of these pins.</p><p>　　The output drive

20、rs on Ports 0 through 3 remain disabled until the Crossbar is enabled by setting XBARE (XBR2.6) to a logic 1.</p><p>　　The output mode of each port pin can be configured as either Open-Drain or Push-Pull; th

21、e default state is Open-Drain. In the Push-Pull configuration, writing a logic 0 to the associated bit in the Port Data register will cause the Port pin to be driven to GND, and writing a logic 1 will cause the Port pin

22、to be driven to VDD. In the Open-Drain configuration, writing a logic 0 to the associated bit in the Port Data register will cause the Port pin to be driven to GND, and a logic 1 will cause th</p><p>　　The o

23、utput modes of the Port pins on Ports 0 through 3 are determined by the bits in the associated PnMDOUT registers (See Figure 17.11, Figure 17.14, Figure 17.16, and Figure 17.18). For example, a logic 1 in P3MDOUT.7 will

24、configure the output mode of P3.7 to Push-Pull; a logic 0 in P3MDOUT.7 will configure the output mode of P3.7 to Open-Drain. All Port pins default to Open-Drain output.</p><p>　　The PnMDOUT registers control

25、 the output modes of the port pins regardless of whether the Crossbar has allocated the Port pin for a digital peripheral or not. The exceptions to this rule are: the Port pins connected to SDA, SCL, RX0 (if UART0 is in

26、Mode 0), and RX1 (if UART1 is in Mode 0) are always configured as Open-Drain outputs, regardless of the settings of the associated bits in the PnMDOUT registers.</p><p>　　A Port pin is configured as a digita

27、l input by setting its output mode to “Open-Drain” and writing a logic 1 to the associated bit in the Port Data register. For example, P3.7 is configured as a digital input by setting P3MDOUT.7 to a logic 0 and P3.7 to a

28、 logic 1.</p><p>　　If the Port pin has been assigned to a digital peripheral by the Crossbar and that pin functions as an input (for example RX0, the UART0 receive pin), then the output drivers on that pin a

29、re automatically disabled.</p><p>　　In addition to the external interrupts /INT0 and /INT1, whose Port pins are allocated and assigned by the Crossbar, P3.6 and P3.7 can be configured to generate edge sensit

30、ive interrupts; these interrupts are configurable as falling- or rising-edge sensitive using the IE6CF (P3IF.2) and IE7CF (P3IF.3) bits. When an active edge is detected on P3.6 or P3.7, a corresponding External Interrupt

31、 flag (IE6 or IE7) will be set to a logic 1 in the P3IF register (See Figure 17.19). If the associated interr</p><p>　　By default, each Port pin has an internal weak pull-up device enabled which provides a r

32、esistive connection (about 100 k兦) between the pin and VDD. The weak pull-up devices can be globally disabled by writing a logic 1 to the Weak Pull-up Disable bit, (WEAKPUD,XBR2.7). The weak pull-up is automatically deac

33、tivated on any pin that is driving a logic 0; that is, an output pin will not contend with its own pull-up device. The weak pull-up device can also be explicitly disabled on a Port 1 pin by co</p><p>　　The p

34、ins on Port 1 can serve as analog inputs to the ADC1 analog MUX. A Port pin is configured as an Analog Input by writing a logic 0 to the associated bit in the P1MDIN register (see Figure 17.13). All Port pins default to

35、a Digital Input mode. Configuring a Port pin as an analog input:</p><p>　　1.Disables the digital input path from the pin. This prevents additional power supply current from being drawn when the voltage at th

36、e pin is near VDD / 2. A read of the Port Data bit will return a logic 0 regardless of the voltage at the Port pin.</p><p>　　2.Disables the weak pull-up device on the pin.</p><p>　　3.Causes the

37、Crossbar to “skip over” the pin when allocating Port pins for digital peripherals.</p><p>　　If the External Memory Interface (EMIF) is enabled on the Low ports (Ports 0 through 3), EMIFLE (XBR2.1) should be

38、set to a logic 1 so that the Crossbar will not assign peripherals to P0.7 (/WR), P0.6 (/RD), and if the External Memory Interface is in Multiplexed mode, P0.5 (ALE).</p><p>　　If the External Memory Interface

39、 is enabled on the Low ports and an off-chip MOVX operation occurs, the External Memory Interface will control the output states of the affected Port pins during the execution phase of the MOVX instruction, regardless of

40、 the settings of the Crossbar registers or the Port Data registers. The output configuration of the Port pins is not affected by the EMIF operation, except that Read operations will explicitly disable the output drivers

41、on the Data Bus.</p><p>　　In this example, we configure the Crossbar to allocate Port pins for UART0, the SMBus, UART1, /INT0, and /INT1 (8 pins total). Additionally, we configure the External Memory Interfa

42、ce to operate in Multiplexed mode and to appear on the Low ports. Further, we configure P1.2, P1.3, and P1.4 for Analog Input mode so that the voltages at these pins can be measured by ADC1. The configuration steps are a

43、s follows:</p><p>　　1.XBR0, XBR1, and XBR2 are set such that UART0EN = 1, SMB0EN = 1, INT0E = 1, INT1E = 1, and EMIFLE = 1. Thus: XBR0 = 0x05, XBR1 = 0x14, and XBR2 = 0x02.</p><p>　　2.We configu

44、re the External Memory Interface to use Multiplexed mode and to appear on the Low ports. PRTSEL = 0, EMD2 = 0.</p><p>　　3.We configure the desired Port 1 pins to Analog Input mode by setting P1MDIN to 0xE3 (

45、P1.4, P1.3, and P1.2 are Analog Inputs, so their associated P1MDIN bits are set to logic 0).</p><p>　　4.We enable the Crossbar by setting XBARE = 1: XBR2 = 0x46.</p><p>　　-UART0 has the highest

46、priority, so P0.0 is assigned to TX0, and P0.1 is assigned to RX0.</p><p>　　-The SMBus is next in priority order, so P0.2 is assigned to SDA, and P0.3 is assigned to SCL.</p><p>　　-UART1 is next

47、 in priority order, so P0.4 is assigned to TX1. Because the External Memory Interface is selected on the lower Ports, EMIFLE = 1, which causes the Crossbar to skip P0.6 (/RD) and P0.7 (/WR). Because the External Memory I

48、nterface is configured in Multiplexed mode, the Crossbar will also skip P0.5 (ALE). RX1 is assigned to the next non-skipped pin, which in this case is P1.0.</p><p>　　-/INT0 is next in priority order, so it i

49、s assigned to P1.1.</p><p>　　-P1MDIN is set to 0xE3, which configures P1.2, P1.3, and P1.4 as Analog Inputs, causing the Crossbar to skip these pins.</p><p>　　-/INT1 is next in priority order, s

50、o it is assigned to the next non-skipped pin, which is P1.5.</p><p>　　-The External Memory Interface will drive Ports 2 and 3 (denoted by red dots in Figure 17.6) during the execution of an off-chip MOVX ins

51、truction.</p><p>　　5.We set the UART0 TX pin (TX0, P0.0), UART1 TX pin (TX1, P0.4), ALE, /RD, /WR (P0.[7:3]) outputs to Push-Pull by setting P0MDOUT = 0xF1.</p><p>　　6.We configure the output mo

52、des of the EMIF Ports (P2, P3) to Push-Pull by setting P2MDOUT = 0xFF and P3MDOUT = 0xFF.</p><p>　　7.We explicitly disable the output drivers on the 3 Analog Input pins by setting P1MDOUT = 0x00 (configure o

53、utputs to Open-Drain) and P1 = 0xFF (a logic 1 selects the high-impedance state).</p><p><b>　　附錄2 文獻翻譯</b></p><p>　　C8051F020 （端口輸入/輸出）</p><p>　　C8051F020/1/2/3 MCU 是高集

54、成度的混合信號片上系統(tǒng)，有按8 位端口組織的64 個數(shù)字I/O 引腳（C8051F020/2）或32 個數(shù)字I/O 引腳（C8051F021/3）。低端口（P0、P1、P2 和P3）既可以按位尋址也可以按字節(jié)尋址。高端口（P4、P5、P6 和P7）只能按字節(jié)尋址。所有引腳都耐5V 電壓，都可以被配置為漏極開路或推挽輸出方式和弱上拉。</p><p>　　C8051F020/1/2/3 器件有大量的數(shù)字資源需要通過

55、4 個低端I/O 端口P0、P1、P2 和P3 才能使用。P0、P1、P2 和P3 中的每個引腳既可定義為通用的端口I/O（GPIO）引腳，又可以分配給一個數(shù)字外設(shè)或功能（例如：UART0 或/INT1）。系統(tǒng)設(shè)計者控制數(shù)字功能的引腳分配，只受可用引腳數(shù)的限制。這種資源分配的靈活性是通過使用優(yōu)先權(quán)交叉開關(guān)譯碼器實現(xiàn)的。注意，不管引腳被分配給一個數(shù)字外設(shè)或是作為通用I/O，總是可以通過讀相應(yīng)的數(shù)據(jù)寄存器得到端口I/O 引腳的狀態(tài)。端口1

56、的引腳可以用做ADC1 的模擬輸入。</p><p>　　優(yōu)先權(quán)交叉開關(guān)譯碼器，或稱為“交叉開關(guān)”，按優(yōu)先權(quán)順序?qū)⒍丝? – 3 的引腳分配給器件上的數(shù)字外設(shè)（UART、SMBus、PCA、定時器等）。端口引腳的分配順序是從P0.0 開始，可以一直分配到P3.7。為數(shù)字外設(shè)分配端口引腳的優(yōu)先權(quán)順序列于圖17.3，UART0 具有最高優(yōu)先權(quán)，而CNVSTR 具有最低優(yōu)先權(quán)。</p><p>

57、　　當(dāng)交叉開關(guān)配置寄存器XBR0、XBR1 和XBR2 中外設(shè)的對應(yīng)使能位被設(shè)置為邏輯‘1’時，交叉開關(guān)將端口引腳分配給外設(shè)，如圖17.7、圖17.8 和圖17.9 所示。例如，如果UART0EN位（XBR0.2）被設(shè)置為邏輯‘1’，則TX0 和RX0 引腳將分別被分配到P0.0 和P0.1。因為UART0有最高優(yōu)先權(quán)，所以當(dāng)UART0EN 位被設(shè)置為邏輯‘1’時其引腳將總是被分配到P0.0 和P0.1。如果一個數(shù)字外設(shè)的使能位未被設(shè)置

58、為邏輯‘1’，則其端口將不能通過器件的端口引腳被訪問。注意：當(dāng)選擇了串行通信外設(shè)（即SMBus、SPI 或UART）時，交叉開關(guān)將為所有相關(guān)功能分配引腳。例如，不能為UART0 功能只分配TX0 引腳而不分配RX0 引腳。被使能的外設(shè)的每種組合導(dǎo)致唯一的器件引腳分配。</p><p>　　端口0-3 中所有未被交叉開關(guān)分配的引腳都可以作為通用I/O（GPI/O）引腳，通過讀或?qū)懴鄳?yīng)的端口數(shù)據(jù)寄存器訪問，這是一組既

59、可以按位尋址也可以按字節(jié)尋址的SFR。被交叉開關(guān)分配的那些端口引腳的輸出狀態(tài)受使用這些引腳的數(shù)字外設(shè)的控制。向端口數(shù)據(jù)寄存器（或相應(yīng)的端口位）寫入時對這些引腳的狀態(tài)沒有影響。</p><p>　　不管交叉開關(guān)是否將引腳分配給外設(shè)，讀一個端口數(shù)據(jù)寄存器（或端口位）將總是返回引腳本身的邏輯狀態(tài)。唯一的例外發(fā)生在執(zhí)行讀-修改-寫指令（ANL、ORL、XRL、CPL、INC、DEC、DJNZ、JBC、CLR、SET 和位

60、寫操作）期間。在讀-修改-寫指令的讀周期，所讀的值是端口數(shù)據(jù)寄存器的內(nèi)容，而不是端口引腳本身的狀態(tài)。</p><p>　　因為交叉開關(guān)寄存器影響器件外設(shè)的引腳分配，所以它們通常在外設(shè)被配置前由系統(tǒng)的初試化代碼配置。一旦配置完畢，將不再對其重新編程。</p><p>　　交叉開關(guān)寄存器被正確配置后，通過將XBARE（XBR2.6）設(shè)置為邏輯‘1’來使能交叉開關(guān)。在XBARE 被設(shè)置為邏輯‘1

61、’之前，端口0-3 的輸出驅(qū)動器應(yīng)被明確禁止，以防止對交叉開關(guān)寄存器和其它寄存器寫入時在端口引腳上產(chǎn)生爭用。</p><p>　　被交叉開關(guān)分配給輸入信號（例如RX0）的引腳所對應(yīng)的輸出驅(qū)動器應(yīng)被明確禁止；以保證端口數(shù)據(jù)寄存器和PnMDOUT 寄存器的值不影響這些引腳的狀態(tài)。</p><p>　　在XBARE（XBR2.6）被設(shè)置為邏輯‘1’之前，端口0-3 的輸出驅(qū)動器保持禁止?fàn)顟B(tài)。&l

62、t;/p><p>　　每個端口引腳的輸出方式都可被配置為漏極開路或推挽方式，缺省狀態(tài)為漏極開路。在推挽方式，向端口數(shù)據(jù)寄存器中的相應(yīng)位寫邏輯‘0’將使端口引腳被驅(qū)動到GND，寫邏輯‘1’將使端口引腳被驅(qū)動到VDD。在漏極開路方式，向端口數(shù)據(jù)寄存器中的相應(yīng)位寫邏輯‘0’將使端口引腳被驅(qū)動到GND，寫邏輯‘1’將使端口引腳處于高阻狀態(tài)。當(dāng)系統(tǒng)中不同器件的端口引腳有共享連接，即多個輸出連接到同一個物理線時（例如SMBus

63、連接中的SDA 信號），使用漏極開路方式可以防止不同器件之間的爭用。</p><p>　　端口0-3 引腳的輸出方式由PnMDOUT 寄存器中的對應(yīng)位決定。例如P3MDOUT.7 為邏輯‘1’時將P3.7 配置為推挽方式；P3MDOUT.7為邏輯‘0’時將P3.7 配置為漏極開路方式。所有端口引腳的缺省方式均為漏極開路。</p><p>　　不管交叉開關(guān)是否將端口引腳分配給某個數(shù)字外設(shè)，端

64、口引腳的輸出方式都受PnMDOUT寄存器控制。例外情況是：連接到SDA、SCL、RX0（如果UART0 工作于方式0）、RX1（如果UART1 工作于方式0）的端口引腳總是被配置為漏極開路輸出，而與PnMDOUT 寄存器中的對應(yīng)位的設(shè)置值無關(guān)。</p><p>　　通過設(shè)置輸出方式為“漏極開路”并向端口數(shù)據(jù)寄存器中的相應(yīng)位寫‘1’將端口引腳配置為數(shù)字輸入。例如，設(shè)置P3MDOUT.7 為邏輯‘0’并設(shè)置P3.7

65、為邏輯‘1’即可將P3.7 配置為數(shù)字輸入。</p><p>　　如果一個端口引腳被交叉開關(guān)分配給某個數(shù)字外設(shè)，并且該引腳的功能為輸入（例如UART0 的接收引腳RX0），則該引腳的輸出驅(qū)動器被自動禁止。</p><p>　　除了外部中斷/INT0和/INT1（其引腳由交叉開關(guān)分配）之外，P3.6和P3.7可被配置為邊沿觸發(fā)的中斷源，用IE6CF（P3IF.2）和IE7CF（P3IF.3）

66、位可以將這兩個中斷源配置為下降沿或上升沿觸發(fā)。當(dāng)檢測到P3.6或P3.7有下降沿或上升沿發(fā)生時，P3IF寄存器（見圖4.36）中對應(yīng)的外部中斷標(biāo)志（IE6或IE7）將被置‘1’。如果對應(yīng)的中斷被允許，將會產(chǎn)生一個中斷，CPU將轉(zhuǎn)向?qū)?yīng)的中斷向量地址。</p><p>　　每個端口引腳都有一個內(nèi)部弱上拉部件，在引腳與VDD 之間提供阻性連接（約100 kΩ），在缺省情況下該上拉器件被使能。弱上拉部件可以被總體禁止，

67、通過向弱上拉禁止位（WEAKPUD，XBR2.7）寫‘1’實現(xiàn)。當(dāng)任何引腳被驅(qū)動為邏輯‘0’時，弱上拉自動取消；即輸出引腳不能與其自身的上拉部件沖突。對于端口1 的引腳，將引腳配置為模擬輸入時上拉部件也被禁止，見下面的說明。</p><p>　　端口1 的引腳可以用作ADC1 模擬多路開關(guān)的模擬輸入。通過向P1MDIN 寄存器中的對應(yīng)位寫‘0’即可將端口引腳配置為模擬輸入。缺省情況下端口引腳為數(shù)字輸入方式。將一個

68、端口引腳配置為模擬輸入的過程如下：</p><p>　　1． 禁止引腳的數(shù)字輸入路徑。這可以防止在引腳上的電壓接近VDD / 2 時消耗額外的電源電流。讀端口數(shù)據(jù)為將返回邏輯‘0’，與加在引腳上的電壓無關(guān)。</p><p>　　2． 禁止引腳的弱上拉部件。</p><p>　　3． 使交叉開關(guān)在為數(shù)字外設(shè)分配引腳時跳過該引腳。</p><p>

69、;　　如果外部存儲器接口（EMIF）被設(shè)置在低端口（端口0-3），EMIFLE（XBR2.1）位應(yīng)被設(shè)置為邏輯‘1’，以使交叉開關(guān)不將P0.7 (/WR)、P0.6 (/RD)和P0.5 (/ALE)（如果外部存儲器接口使用復(fù)用方式）分配給外設(shè)。</p><p>　　如果外部存儲器接口被設(shè)置在低端口并且發(fā)生一次片外MOVX 操作，則在該MOVX 指令執(zhí)行期間外部存儲器接口將控制有關(guān)端口引腳的輸出狀態(tài)，而不管交叉開

70、關(guān)寄存器和端口數(shù)據(jù)寄存器的設(shè)置如何。端口引腳的輸出配置不受EMIF 操作的影響，但讀操作將禁止數(shù)據(jù)總線上的輸出驅(qū)動器。</p><p>　　在本例中，我們將配置交叉開關(guān)，為UART0、SMBus、UART1、/INT0 和/INT1分配端口引腳（共8 個引腳）。另外，我們將外部存儲器接口配置為復(fù)用方式并使用低端口。我們還將P1.2、P1.3 和P1.4 配置為模擬輸入，以便用ADC1 測量加在這些引腳上的電壓。配

71、置步驟如下：</p><p>　　1． 按UART0EN = 1、UART1E = 1、SMB0EN = 1、INT0E = 1、INT1E = 1 和EMIFLE =1設(shè)置XBR0、XBR1 和XBR2，則有：XBR0 = 0x05，XBR1 = 0x14，XBR2 = 0x06。</p><p>　　2． 將外部存儲器接口配置為復(fù)用方式并使用低端口，有：PRTSEL = 0，EMD2

72、= 0。</p><p>　　3． 將作為模擬輸入的端口1 引腳配置為模擬輸入方式：設(shè)置P1MDIN 為0xE3（P1.4、P1.3 和P1.2 為模擬輸入，所以它們的對應(yīng)P1MDIN 被設(shè)置為邏輯‘0’）。</p><p>　　4． 設(shè)置XBARE = 1 以使能交叉開關(guān)：XBR2= 0x46。</p><p>　　- UART0 有最高優(yōu)先權(quán)，所以P0.0 被分

73、配給TX0，P0.1 被分配給RX0。</p><p>　　- SMBus 的優(yōu)先權(quán)次之，所以P0.2 被分配給SDA，P0.3 被分配給SCL。</p><p>　　- 接下來是UART1，所以P0.4 被分配給TX1。由于外部存儲器接口選在低端口（EMIFLE = 1），所以交叉開關(guān)跳過P0.6(/RD)和P0.7(/WR)。又因為外部存儲器接口被配置為復(fù)用方式，所以交叉開關(guān)也跳過P0

74、.5(ALE)。下一個未被跳過的引腳P1.0 被分配給RX1。</p><p>　　- 接下來是/INT0，被分配到引腳P1.1。</p><p>　　- 將P1MDIN 設(shè)置為0xE3，使P1.2、P1.3 和P1.4 被配置為模擬輸入，導(dǎo)致交叉開關(guān)跳過這些引腳。</p><p>　　- 在執(zhí)行對片外操作的MOVX 指令期間，外部存儲器接口將驅(qū)動端口2 和端口3（

75、由圖17.6 中的紅點表示）。</p><p>　　5． 我們將UART0 的TX 引腳、UART1 的TX 引腳（TX1，P0.4）、ALE、/RD、/WR（P0.[7:3]）的輸出設(shè)置為推挽方式，通過設(shè)置P0MDOUT = 0xF1 來實現(xiàn)。</p><p>　　6． 我們通過設(shè)置P2MDOUT = 0xFF 和P3MDOUT = 0xFF 將EMIF 端口（P2、P3）的輸出方式配置