基于ieee802.16e標(biāo)準(zhǔn)的ldpc碼性能分析及硬件實(shí)現(xiàn)

1、華中科技大學(xué)碩士學(xué)位論文基于IEEE802.16e標(biāo)準(zhǔn)的LDPC碼性能分析及硬件實(shí)現(xiàn)姓名：王衛(wèi)明申請(qǐng)學(xué)位級(jí)別：碩士專業(yè)：通信與信息系統(tǒng)指導(dǎo)教師：彭立20090524II 華 中 科 技 大 學(xué) 碩 士 學(xué) 位 論 文 Abstract Low-density parity-check (LDPC) codes have received more and more attention because of its excellent

2、design performance and very low decoding complexity. It is the most successful channel code that approaches Shannon’s capacity limit, also is the main optional channel code for the next generation wireless communication

3、systems. Imbursed by the Program of National Natural Science Fund “Research of the algebra structure algorithm of the high performance and low complexity LDPC code” and the Program of Natural Science Fund of Hubei provin

4、ce “Molding for the bit-flipping decoding algorithm of LDPC code based on iterative signal processing technology”, this thesis makes an in-depth research on encoder arithmetic and iterative decoder performance analysis o

5、f LDPC code in IEEE802.16e standard. Firstly, this thesis summarizes the course and development of channel code and the main research fields, then, briefly introduces the basic theory of LDPC code. Then the thesis promot

6、es extrinsic information transfer (EXIT) chart as the analysis and optimize tool for LDPC decoder. After modeling the message exchange of the weight LDPC decoder and making use of the new scheme of the degree distributio

7、n of the basic matrix, the thesis compare the performance of all code rate LDPC codes based on EXIT chart. Then the paper found codes with different rate but has the same code length have uniform EXIT chart, so as the D

8、and Q that permute the identity matrix of the basic matrix in IEEE802.16e standard. So，we can simply analyze the convergence performance of iterative decoder of LDPC code based on EXIT chart and find the better structure

9、 LDPC code. Finally, with the combination of analysis of the structure of the basic matrix in IEEE802.16e standard and RU fast-speed encoder arithmetic, the paper introduces the hardware architecture of LDPC encoder in I

10、EEE802.16e standard. This paper innovatively promotes a new matrix storage scheme and reduced the complexity of encoder hardware realization based on the analysis of the structure of the basic matrix. Using the hardware

11、description language, the paper implements the FPGA design of the LDPC code of code length 576 and code rate 1/2 in IEEE802.16e standard. The simulation results indicate that the encoder hardware architecture can meet th