ep4ce22官方原理圖解

1、5544332211D DC CB BA A04 ~ 08SCHEMATICALTERA Cyclone IV Development & Education Board (DE0-Nano)CONTENT Cover Page, Placement,TOP05 POWER SDRAM, EEPROM CLOCK, LED, BUTTON,SW, GPIOs, 2X13 HEADER, G-SENSOR, ADC 02 EP4

2、CE22POWER 1.2V, 2.5V, 3.3V 04 MEMORY 03 IN/OUT 09 ~ 1101 TOP 01 ~ 0314 12 ~ 13PAGECyclone IV EP4CE22 BANK1..BANK8 , POWER , CONFIGTitleSize Document Number RevDate: Sheet ofCopyright (c) 2007 by Terasic Technologies Inc.

3、 Taiwan.No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.COVER PAGE CDE0-Nano BoardB1 14 Thursday, July 12, 2012TitleSize Documen

4、t Number RevDate: Sheet ofCopyright (c) 2007 by Terasic Technologies Inc. Taiwan.No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved

5、.COVER PAGE CDE0-Nano BoardB1 14 Thursday, July 12, 2012TitleSize Document Number RevDate: Sheet ofCopyright (c) 2007 by Terasic Technologies Inc. Taiwan.No part of this schematic design may be reproduced, duplicated, or

6、 used without the prior written permission of Terasic.All rights reserved.COVER PAGE CDE0-Nano BoardB1 14 Thursday, July 12, 20125544332211D DC CB BA ADRAM_ADDR[12..0] DRAM_DQM[1..0]DRAM_DQ[15..0]DRAM_DQ[15..0] DRAM_ADDR

7、[12..0] DRAM_DQM[1..0]KEY[1..0]SW[3..0]LED[7..0]KEY[1..0]SW[3..0]LED[7..0] DRAM_BA0 DRAM_BA1 DRAM_CAS_N DRAM_RAS_N DRAM_WE_N DRAM_CS_N DRAM_CKE DRAM_CLKDRAM_BA0 DRAM_BA1 DRAM_CAS_N DRAM_RAS_N DRAM_WE_N DRAM_CS_N DRAM_CKE

8、 DRAM_CLKJTAG_TMS JTAG_TCK JTAG_TDI JTAG_TDONSTATUS CONF_DONE NCONFIG NCEI2C_SCLK I2C_SDATG_SENSOR_CS_N G_SENSOR_INTCLOCK_50I2C_SCLK I2C_SDATI2C_SCLK I2C_SDATG_SENSOR_CS_N G_SENSOR_INTADC_SDAT ADC_CS_N ADC_SADDR ADC_SCLK

9、CLOCK_50GPIO_0_IN[1..0] GPIO_0[33..0]GPIO_1_IN[1..0] GPIO_1[33..0]GPIO_2_IN[2..0] GPIO_2[12..0]ADC_SDAT ADC_CS_N ADC_SADDR ADC_SCLKTitleSize Document Number RevDate: Sheet ofCopyright (c) 2007 by Terasic Technologies Inc

10、. Taiwan.No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.TOP CDE0-Nano BoardB3 14 Thursday, July 12, 2012TitleSize Document Numb

11、er RevDate: Sheet ofCopyright (c) 2007 by Terasic Technologies Inc. Taiwan.No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.All rights reserved.TOP C

12、DE0-Nano BoardB3 14 Thursday, July 12, 2012TitleSize Document Number RevDate: Sheet ofCopyright (c) 2007 by Terasic Technologies Inc. Taiwan.No part of this schematic design may be reproduced, duplicated, or used without

13、 the prior written permission of Terasic.All rights reserved.TOP CDE0-Nano BoardB3 14 Thursday, July 12, 2012PAGE 4 - 802 EP4CE22NSTATUSNCENCONFIGTDITMSTDOTCKCONF_DONELED[7..0]SW[3..0]ADC_SCLKKEY[1..0]CLOCK_50DRAM_BA0 DR

14、AM_BA1DRAM_CKE DRAM_CLKDRAM_ADDR[12..0] DRAM_DQ[15..0]DRAM_DQM[1..0]G_SENSOR_INTDRAM_CAS_NADC_SADDRDRAM_WE_N DRAM_CS_NADC_CS_NG_SENSOR_CS_NADC_SDATDRAM_RAS_NI2C_SDAT I2C_SCLKGPIO_1_IN[1..0]GPIO_0[33..0]GPIO_2_IN[2..0]GPI

15、O_1[33..0]GPIO_0_IN[1..0]GPIO_2[12..0]PAGE 12 - 1304 MEMORYDRAM_DQM[1..0]DRAM_DQ[15..0] DRAM_ADDR[12..0]DRAM_CLK DRAM_CKEDRAM_BA0 DRAM_BA1 DRAM_CAS_NDRAM_CS_N DRAM_WE_N DRAM_RAS_NI2C_SDAT I2C_SCLKPAGE 1405 POWERPAGE 9 -