基于quartusii以及74ls192為核心的簡(jiǎn)易數(shù)字時(shí)鐘設(shè)計(jì)

1、基于 基于 QuartusII 以及 以及 74ls192 為核 為核心的簡(jiǎn)易數(shù)字時(shí)鐘設(shè)計(jì) 心的簡(jiǎn)易數(shù)字時(shí)鐘設(shè)計(jì)該項(xiàng)目是利用 QuartusII 軟件設(shè)計(jì)一個(gè)數(shù)字鐘，進(jìn)行試驗(yàn)設(shè)計(jì)和仿真調(diào)試，實(shí)現(xiàn)了計(jì)時(shí)，校時(shí)，校分，保持和整點(diǎn)報(bào)時(shí)功能，并下載到 FPGA 實(shí)驗(yàn)系統(tǒng)中進(jìn)行調(diào)試和驗(yàn)證。此外還添加了顯示星期，使得設(shè)計(jì)的數(shù)字鐘的功能更加完善。關(guān)鍵字：QuartusII EDA FPGA 數(shù)字鐘 74ls192 This This experi

2、ment experiment is is to to design design a digital digital clock clock using using QuartusII QuartusII software, software, debugging debugging test test design design and and simulation, simulation, to to achieve ac

3、hieve timing, timing, timing, timing, school school hours, hours, maintain maintain and and the the whole whole point point timekeeping timekeeping function, function, and and download download the the debugging d

4、ebugging and and verification verification of of FPGA FPGA experimental experimental system. system. In In addition addition also also added added that that week, week, making making digital digital clock clock des

5、ign design features features more more perfect. perfect.Keywords: Keywords: QuartusII QuartusII EDA EDA FPGA FPGA 74LS192 74LS192 digital digital clock clock的 50Mhz 的頻率分成電路所需要的頻率來(lái)使用；計(jì)時(shí)電路將與靜、動(dòng)態(tài)顯示電路相連，將時(shí)間與星期顯示在七段數(shù)碼管上，

6、保持電路作用時(shí)，系統(tǒng)停止計(jì)時(shí)并保持時(shí)間不變。其原理框圖如圖所示：三、 三、各模塊設(shè)計(jì)的說(shuō)明 各模塊設(shè)計(jì)的說(shuō)明1．分頻模塊 ．分頻模塊我實(shí)現(xiàn)分頻的方法是采用多個(gè) 74ls192 對(duì) 50MHz 的平率進(jìn)行計(jì)數(shù)，由于 74ls192 每計(jì)十個(gè)脈沖從進(jìn)位輸出一個(gè)脈沖，下一個(gè) 74ls192計(jì)上一個(gè) 74ls192 進(jìn)位端輸出一的個(gè)脈開(kāi)始計(jì)，相當(dāng)于下一個(gè) 74ls192計(jì)了 100 個(gè)脈沖才輸出一個(gè)脈沖，下一個(gè)計(jì) 1000 次才輸出一個(gè)脈沖，考