validation and testing of design hardening for single event effects using the 8051 microcontroller

1、 Abstract - With the dearth of dedicated radiation hardened foundries, new and novel techniques are being developed for hardening designs using non-dedicated foundry services. In this paper, we will discuss the implic

2、ations of validating these methods for the single event effects (SEE) in the space environment. Topics include the types of tests that are required and the design coverage (i.e., design libraries: do they need valida

3、ting for each application?). Finally, an 8051 microcontroller core from NASA Institute of Advanced Microelectronics (IAµE) CMOS Ultra Low Power Radiation Tolerant (CULPRiT) design is evaluated for SEE mitig

4、ative techniques against two commercial 8051 devices.Index Terms – Single Event Effects, Hardened-By-Design, microcontroller, radiation effects. I. INTRODUCTION NASA constantly strives to provide the best capture of

5、science while operating in a space radiation environment using a minimum of resources [1,2]. With a relatively limited selection of radiation-hardened microelectronic devices that are often two or more generations of

6、 performance behind commercial state-of- the-art technologies, NASA’s performance of this task is quite challenging. One method of alleviating this is by the use of commercial foundry alternatives with no or minimally

7、 invasive design techniques for hardening. This is often called hardened-by-design (HBD). Building custom-type HBD devices using design James W. Howard Jr. is with Jackson what types of tests are required for HBD val

8、idation? II. TESTING HBD DEVICES CONSIDERATIONS Test methodologies in the United States exist to qualify individual devices through standards and organizations such as ASTM, JEDEC, and MIL-STD- 883. Typically, TID (Co-

9、60) and SEE (heavy ion and/or proton) are required for device validation. So what is unique to HBD devices? As opposed to a “regular” commercial-off-the-shelf (COTS) device or application specific integrated circuit

10、 (ASIC) where no hardening has been performed, one needs to determine how validated is the design library as opposed to determining the device hardness. That is, by using test chips, can we “qualify” a future device

11、using the same library? Consider if Vendor A has designed a new HBD library portable to foundries B and C. A test chip is designed, tested, and deemed acceptable. Nine months later a NASA flight project enters the mi

12、x by designing a new device using Vendor A’s library. Does this device require complete radiation qualification testing? To answer this, other questions must be asked. How complete was the test chip? Was there suffic

13、ient statistical coverage of all library elements to validate each cell? If the new NASA design uses a partially or insufficiently characterized portion of the design library, full testing might be required. Of cours

14、e, if part of the HBD was relying on inherent radiation hardness of a process, some of the tests (like SEL in the earlier example) may be waived. Other considerations include speed of operation and Validation and Tes

15、ting of Design Hardening for Single Event Effects Using the 8051 MicrocontrollerJames W. Howard Jr., Senior Member, IEEE, Kenneth A. LaBel, Member, IEEE, Martin A. Carts, Member, IEEE, Christina Seidleck, Jody W. Gambl

16、es, Senior Member, IEEE, and Steven L. Ruggles 0-7803-9367-8/05/$20.00 ©2005 IEEE. 0-7803-9367-8/05/$20.00 ©2005 IEEE. 85 85The CULPRiT technology device is a version of the MSC-51 family compatible C8051 HDL

17、core licensed from the Ultra Low Power (ULP) process foundry. The CULPRiT technology C8051 device is designed to operate at a supply voltage of 500 mV and includes an on-chip input/output signal level-shifting interf

18、ace with conventional higher voltage parts. The CULPRiT C8051 device requires two separate supply voltages; the 500 mV and the desired interface voltage. The CULPRiT C8051 is ROMless and is intended to be instructio

19、n set compatible with the MSC-51 family. V. TEST HARDWARE The 8051 Device Under Test (DUT) was tested as a component of a functional computer as illustrated in Figure 1. Aside from DUT itself, the other components of

20、the DUT computer were removed from the immediate area of the irradiation beam. A small card (one per DUT package type) with a unique hard-wired identifier byte contained the DUT, its crystal, and bypass capacitors (a

21、nd voltage level shifters for the CULPRiT DUTs). This “DUT Board“ was connected to the “Main Board“ by a short 60-conductor ribbon cable. The Main Board had all other components required to complete the DUT Computer,

22、 including some which nominally are not necessary in some designs (such as external RAM, external ROM and address latch). Figure 1. Hardware Block Diagram of the Test System. The DUT Computer and the Test Control Com

23、puter were connected via a serial cable and communications were established between the two by the Controller (that runs custom designed serial interface software). This Controller software allowed for commanding of

24、the DUT, downloading DUT Code to the DUT, and real-time error collection from the DUT during and post irradiation. A 1 Hz signal source provided an external watchdog timing signal to the DUT, whose watchdog output wa

25、s monitored via an oscilloscope. The power supply was monitored to provide indication of latchup. VI. TEST SOFTWARE The 8051 test software concept is straightforward. It was designed to be a modular series of small tes

26、t programs each exercising a specific part of the DUT (Figure 2). Since each test was stand alone, they were loaded independently of each other for execution on the DUT. This ensured that only the desired portion of

27、the 8051 DUT was exercised during the test and helped pinpoint location of errors that occur during testing. All test programs resided on the controller PC until loaded via the serial interface to the DUT computer. I

28、n this way, individual tests could have been modified at any time without the necessity of burning PROMs. Additional tests could have also been developed and added without impacting the overall test design. The only

29、 permanent code, which was resident on the DUT, was the boot code and serial code loader routines that established communications between the controller PC and the DUT. Figure 2. Test Software Block Diagram. All test

30、programs implemented: ? An external Universal Asynchronous Receive and Transmit device (UART) for transmission of error information and communication to controller computer. ? An external real-time clock for data