外文翻譯---基于fpga的數(shù)字基帶信號(hào)的矢量信號(hào)分析（英文）

1、VECTOR SIGNAL ANALYSIS OF DIGITAL BASEBAND AND IF SIGNALS WITHIN AN FPGA Scott Ferguson Agilent Technologies, Inc 1900 Garden of the Gods Rd. Colorado Springs, CO 80907 USA +1 719 590-2403 sferguson@agilent.com Abs

2、tract - This paper introduces novel techniques for analyzing digital signal and modulation quality inside of Field Programmable Gate Arrays (FPGAs). This convergence of innovations in logic analysis with th

3、ose in vector signal analysis can provide designers of digital Baseband and IF signal processing systems as well as analog- to-digital and digital-to-analog converters with the ability to make key measurements where

4、they were previously unavailable or difficult to make.As FPGAs continue to make larger contributions in DSP for wireless and satellite communications, the increasing dominance of digital Baseband and IF signals

5、presents a challenge to designers of radio and satellite systems. DSP circuit designers constantly make tradeoffs between design complexity (bit precision, number of filter taps, etc), power consumption, and signa

6、l quality. Key measurements like Error Vector Magnitude can be used to gauge the performance implications of these tradeoffs. Previously, vector signal analysis measurements have been either directly integrated in

7、to RF test instruments, or written as custom software by Baseband designers. With entire sections of a radio being implemented digitally, and integrated inside a single chip, new methods are needed to characteri

8、ze the individual subsystems in a digital radio. This paper presents the combination of a dynamic FPGA probe, which enables routing of signal groups within an FPGA to a logic analyzer for measurement through a small

9、 number of physical package pads, with an FFT-based vector signal analysis software package. This combination provides simultaneous measurement of time domain, frequency spectrum, and modulation quality on digital

10、 signals inside an FPGA. It also provides the quick selection of various internal nets for signal analysis without time- consuming redesigns of the FPGA. INTRODUCTIONField Programmable Gate Arrays (FPGAs) are in wides

11、pread use for digital signal processing (DSP) in wireless, aerospace, and defense applications. Their programmability enables designers to build early prototype systems while specifications are still changing, as

12、well as to support multiple communication technologies with a single hardware design. Their increasing performance enables digital processing of increasingly wider bandwidths, improving signal quality while redu

13、cing power consumption and material cost. As an increasing portion of a transceiver is digital, the number of probe points for analog spectrum and vector signal analysis is decreasing. Digital signal processing syste

14、ms possess the ability to create near-perfect signal quality due to the lack of noise and nonlinearities associated with analog signal processing. However, tradeoffs are constantly made in signal quality in DSP syst

15、ems to meet requirements in system cost, power consumption, and time to market. For this reason, signal analysis on digital components and sub-components is needed to view the relative impact of design tradeoffs on s

16、ignal quality. Error Vector Magnitude (EVM) has been a popular metric for modulated signal quality for many 402 0-7803-9101-2/05/$20.00 ©2005 IEEEfeature, and provide 48 signals through 24 pins (for example I will

17、 be clocked on the rising clock edge, and Q will be transferred on the falling edge).After the mux core is compiled into the FPGA program, the logic analyzer controls the FPGA via the JTAG interface. When the user sele

18、cts a group (or bank) of signals to view, a message is sent via JTAG to the FPGA to configure the switch. At the same time the logic analyzer is reconfigured with new signal names, to match the net names of the signal

19、s now being probed. This switch configuration makes no changes to signal routing, meaning that circuit timing is not impacted.Previously, interactive debug of FPGA signals inside a large design required development of a

20、custom mux by the end user, or many hours of recompiling a design to select different signals to connect to the debug port. If not performed carefully, a recompile of an FPGA design could also impact circuit timing, and

21、cause problems to appear or disappear. Using the dynamic probe saves compile time and eliminates the risk of timing changes.The logic analyzer can then capture signal data from all 88 internal nets (48 at a time) using

22、25 pins, and 25 logic analyzer channels.Digital Signals vs Digitized Signals While many signals are digital, the signals in a DSP circuit are digital representations of soon-to- become or recently-digitized analog signal

23、s. This can be visualized using the logic analyzer’s chart display capabilities, as seen in Figure 3. Using a two’s complement representation, the 8-bit value for I and Q symbols resemble an analog waveform, shown in th

24、e top row of the display. The same trace in a traditional bus style display is shown in the lower portion of the figure. Figure 3 - Chart Display of Digital BusOther interesting time domain analysis can be done with a l

25、ogic analyzer, such as measuring the group delay of the RRC filter. In Figure 4, The “I” symbol stream is captured before and after the RRC filter (named “i_symbol” and “i_baseband”, respectively). The group delay can

26、be measured using markers and a visual inspection of the signals. In the figure, the center of a wide flat spot is marked in both rows, and the time interval measurement of 250 nanoseconds is shown on the upper left por

27、tion of the screen.Figure 4 - Time Domain Signal AnalysisDigital Vector Signal AnalysisBeyond verification of smooth waveforms and time interval measurements, a logic analyzer does not typically provide much more signal

28、analysis capability. Users have been left to make their own custom analysis tools, linking the instrument to their own software packages or commercial mathematics tools. While this is time consuming, it also adds risk t