函數(shù)發(fā)生器外文文獻及翻譯

1、<p><b>　　外文文獻1原文：</b></p><p>　　DDS devices to produce high-quality waveform: a simple, efficient and flexible</p><p><b>　　Summary</b></p><p>　　Direct di

2、gital frequency synthesis (DDS) technology for the generation and regulation of high-quality waveforms, widely used in medical, industrial, instrumentation, communications, defense and many other areas. This article will

3、 briefly describe the technology, on its strengths and weaknesses, examine some application examples, and also introduced some new products that contribute to the promotion</p><p>　　Introduction</p>&

4、lt;p>　　A key requirement in many industries is an exact production, easy operation and quick change of different frequencies, different types of waveforms. Whether it is broadband transceiver requires low phase noise

5、and excellent spurious-free dynamic performance of agile frequency source, or for industrial measurement and control system needs a stable frequency excitation, fast, easy and economical to produce adjustable waveform wh

6、ile maintaining phase continuity capabilities are critical to a design</p><p>　　Frequency synthesis task</p><p>　　The growing congestion of the spectrum, coupled with lower power consumption, qu

7、ality of never-ending demand for higher measuring equipment, these factors require the use of the new frequency range, requires a better use of existing frequency range. A result, the search for better control, in most c

8、ases, by means of frequency synthesizer for frequency generation. These devices use a given frequency, fC of to generate a target frequency (and phase) fOUT the general relationship can be simply expr</p><p>

9、;　　fOUT = εx× fC</p><p>　　Among them, the scale factor εx, sometimes known as the normalized frequency.</p><p>　　The equation is usually gradual approximation of the real number algorithms.

10、 When the scale factor is a rational number, two relatively prime numbers (output frequency and reference frequency) than the harmonic. However, in most cases, εx may belong to a broader set of real numbers, the approxim

11、ation process is within the acceptable range will be truncated</p><p>　　Direct Digital Frequency Synthesizer</p><p>　　The frequency synthesizer a practical way to achieve is the direct digital f

12、requency synthesis (of DDFS), usually referred to as direct digital synthesis (DDS). This technique using digital data processing to generate a frequency and phase adjustable output, the output anda fixed frequency refer

13、ence clock source fC. related. DDS architecture, the reference or the system clock frequency divided by a scale factor to produce the desired frequency, the scale factor is controlled by the binary tuning</p><

14、p>　　In short, direct digital frequency synthesizer to convert a bunch of clock pulses into an analog waveform, usually a sine wave, triangle wave or square wave. Shown in Figure 1, its main parts: the phase accumulato

15、r (to produce the output waveform phase angle data), relative to digital converter, (above the phase data is converted to the instantaneous output amplitude data), and digital-to-analog converter (DAC) (the magnitude of

16、data into a sampled analog data points)</p><p>　　Figure 1.DDS function of the system block diagram.</p><p>　　For the sine wave output, relative to digital converter is usually a sine lookup tabl

17、e (Figure 2). Phase accumulator unit count N a relative to the frequency of fC, according to the following equation:</p><p>　　The number of pulses of the fC:</p><p>　　M is the resolution of the

18、tuning word (24-48) </p><p>　　N corresponds to the smallest increment of phase change of the phase accumulator output word</p><p>　　Figure 2. Typical DDS architecture and signal path (with DACs)

19、.</p><p>　　Changing N will immediately change the output phase and frequency, so the system has its own continuous phase characteristics, which is one of the key attributes of many applications. No loop sett

20、ling time, which is different from the analog system, such as phase-locked loops (PLLs). DAC is usually a high-performance circuit, designed specifically for the DDS core (phase accumulator and phase amplitude converter)

21、. In most cases, the results of the device (usually single-chip) is generally referr</p><p>　　Actual DDS devices are generally multiple registers, in order to achieve a different frequency and phase modulati

22、on scheme. Such as phase register, their storage phase of increase in the output phase of the phase accumulator. In this way, the corresponding delay output sine wave phase in a phase tuning word. This is useful for phas

23、e modulation applications for communication systems. The resolution of the adder circuit determines the number of bits of the phase tuning word, therefore, also decide</p><p>　　Integrated in a single device

24、on the engine of a DDS and a DAC has both advantages and disadvantages, however, whether integrated or not, need a DAC to produce ultra-high purity high-quality analog signal. DAC will convert digital sinusoidal output t

25、o an analog sine wave may be single-ended or differential. Some of the key requirements for low phase noise, excellent wideband (WB) and narrowband (NB), spurious-free dynamic range (SFDR), and low power consumption. If

26、the external device, the DAC m</p><p>　　DDS and other solutions</p><p>　　The frequency analog phase-locked loops (PLLs), clock generator, and the use of FPGA dynamic programming of the output of

27、 the DAC. By examining the spectrum of performance and power of these technologies, a simple comparison, Table 1 shows the qualitative results of the comparison</p><p>　　Table 1.DDS with competing technologi

28、es - Advanced compare</p><p>　　Phase-locked loop is a feedback loop and its components: a phase comparator, a divider and a pressure-controlled oscillator (VCO), phase comparator reference frequency and outp

29、ut frequency (usually the output frequency is N)frequency) were compared. The error voltage generated by the phase comparator is used to adjust the VCO, thus the output frequency. When the loop is established, the output

30、 frequency and / or phase with the reference frequency to maintain a precise relationship. PLL has long </p><p>　　Table 2 Benchmark Analysis Summary - frequency generation technique (<50 MHz)</p>&

31、lt;p>　　Also be noted that the DDS device for digital methods to produce the output waveform, it can simplify some of the architecture of the solution, or the waveform of digital programming to create the conditions. U

32、sually with a sine wave to explain the functions and working principle of the DDS, but using modern DDS ICs can easily generate a triangle wave or square wave (clock) output, thereby eliminating the former case the looku

33、p table, and the latter case the DAC the need to integrate a simple an</p><p>　　Performance and limitations of the DDS</p><p>　　Image and envelope: Sin (x) xx roll-off</p><p>　　The

34、actual output of the DAC is not a continuous sine wave, but a series of pulses with a sinusoidal time envelope. The corresponding spectrum is a series of image and signal aliasing. Image along the sin (x) / x envelope di

35、stribution (see Figure 3 | margin | graph). The need for the filter to suppress frequencies outside the target band, but can not inhibit the high-level in the passband aliasing (for example, caused due to DAC non-linear)

36、</p><p>　　The Nyquist criterion requires that each cycle requires at least two sampling points in order to rebuild the desired output waveform. The Mirroring response arising from sampling the output frequen

37、cy K, CLOCK × OUT In this example, which CLOCK = 25 25 MHz and fOUT = 5 MHz, the first and second mirror frequency appear in (see Figure 3) fCLOCK × fOUT, ??o 20 MHz and 30 MHz. The third and fourth mirror freq

38、uency at 45 MHz and 55 MHz. Note, sin (x) / x value of zero at multiples of the sampling freq</p><p>　　Sin, in Figure 3.DDS, (x) / x roll-off.</p><p>　　In a typical DDS application, the use of a

39、 low-pass filter to suppress the mirror frequency response of the output spectrum. To make the low-pass filter cutoff frequency to remain at reasonable levels, and keep it simple filter design, a feasible approach is the

40、 use of an economic low-pass output filter bandwidth limited to about 40% of the frequency of clock.Any given mirror frequency relative to the amplitude of the fundamental formula of sin (x) / x calculation. Because the

41、 function of the f</p><p><b>　　Shake</b></p><p>　　The edge of the perfect clock source will be the precise time interval, the interval will never change. Of course, this is not possi

42、ble; even the best oscillator is also the ideal components constitute, with noise and other defects. Quality and low phase noise crystal oscillator jitter picosecond, and is built up from one million the number of clock

43、edge. The factors leading to jitter external interference, thermal noise, the oscillator circuit instability and power, ground and output connection</p><p>　　Noise - including the phase noise</p><

44、p>　　The sampling system noise depends on many factors, the most important factor is the reference clock jitter, this jitter performance of phase noise on fundamental signal. In the DDS system, the register output of t

45、he truncated phase may bring the system error code. The binary word does not lead to the truncation error. But for non-binary word, phase noise truncation error in the spectrum spurious. Spurious frequency / amplitude de

46、pends on the code word. Quantification and linearity error of the D</p><p>　　Application</p><p>　　DDS applications can be divided into two categories:</p><p>　　Require agile frequen

47、cy source for data coding and modulation applications, communications and radar systemsRequire measurement of the universal frequency synthesizer features and programmable tuning, scanning, and motivational skills, indu

48、strial and optical applications</p><p>　　Both cases, the trend toward higher spectral purity (low phase noise and higher spurious free dynamic range), also low power and small size requirements to accommodat

49、e the remote ordemand for battery-powered devices.</p><p>　　Modulation / data encoding, and synchronization of the DDS</p><p>　　DDS products first appeared on the radar and military applications

50、 and the development of some of its characteristics (performance improvements, cost and size, etc.) DDS technology is becoming more prevalent in the modulation and data encoding applications. This section will discuss th

51、e two data encoding scheme in the DDS system.</p><p>　　Binary frequency shift keying (BFSK, or referred to as FSK) one of the most simple form of data encoding.</p><p>　　The launch of the data i

52、s a continuous carrier frequency in two discrete frequency (binary one, ie, pass number, a binary 0, namely, the transformation between the space). Figure 4 shows the relationship between the data and transmit signals.&l

53、t;/p><p>　　Figure 4 binary FSK modulation.</p><p>　　Binary 1 and 0 for two different frequencies f0 and f1, respectively. This encoding scheme can be easily DDS device. On behalf of the output freq

54、uency of the DDS frequency tuning word change to f0 and f1, will launch the 1 and 0. To transform the output frequency shall dedicated pin FSELECT, containing the appropriate tuning word registers (see Figure 5)</p>

55、;<p>　　Figure 5. AD9834 or AD9838 DDS tuning word selector realization of the FSK encoding.</p><p>　　Phase shift keying (PSK) is a simple form of data encoding. In PSK, the carrier frequency remains t

56、he same, by changing the phase of the transmitted signal to transmit information. Can take advantage of a variety of programs to achieve PSK,. The easiest way is often referred to as binary PSK (BPSK), using only two sig

57、nal phase: 0 ° (logic 1) and 180 ° (logic 0). Members state depends on the status of the former one. If the wave phase remains unchanged, the signal state will remain the same (low </p><p>　　The us

58、e of synchronous mode of multiple DDS devices to achieve the I / Q</p><p>　　Multiple DDS components to achieve the many applications of the I / Q sine wave or square wave signal of known phase relationship b

59、etween two or more synchronous mode. A common example is the same phase and quadrature modulation (I / Q) in this technique, the phase angle of 0 ° and 90 ° from the carrier frequency signal information. To run

60、 two separate DDS components, you can use the same source clock to output can directly control and manipulate the signal of the phase relationship. In Figure 6</p><p>　　Figure 6. Synchronize the two DDS comp

61、onents.</p><p>　　Author: Brendan Cronin [brendan.cronin @ analog.com] ADI core products and technologies (CPT), a product marketing engineer. Brendan joined the ADI, in 1998 and worked for six years in the i

62、ndustrial and automotive products sector, as mixed-signal design engineers. Brendan is currently the main linear and related technologies.</p><p><b>　　外文文獻1翻譯：</b></p><p>　　DDS器件產(chǎn)生高質(zhì)

63、量波形：簡單、高效而靈活</p><p>　　摘要 直接數(shù)字頻率合成(DDS)技術(shù)用于產(chǎn)生和調(diào)節(jié)高質(zhì)量波形，廣泛用于醫(yī)學(xué)、工業(yè)、儀器儀表、通信、國防等眾多領(lǐng)域。本文將簡要介紹該技術(shù)，說明其優(yōu)勢和不足，考察一些應(yīng)用示例，同時介紹一些有助于該技術(shù)推廣的新產(chǎn)品。</p><p>　　簡介 許多行業(yè)中一個關(guān)鍵的需求是精確產(chǎn)生、輕松操作并快速更改不同頻率、不同類型的波形。無論是寬帶收發(fā)器

64、要求具有低相位噪聲和出色的無雜散動態(tài)性能的捷變頻率源，還是工業(yè)測量和控制系統(tǒng)需要穩(wěn)定的頻率激勵，快速、輕松、經(jīng)濟地產(chǎn)生可調(diào)波形并同時維持相位連續(xù)性的能力都是至關(guān)重要的一項設(shè)計標(biāo)準(zhǔn)，而這正是直接數(shù)字頻率合成技術(shù)的優(yōu)勢所在。</p><p>　　頻率合成的任務(wù)。 不斷增多的頻譜擁堵，加上對功耗更低、質(zhì)量更高的測量設(shè)備的永無止境的需求，這些因素都要求使用新的頻率范圍，要求更好地利用現(xiàn)有頻率范圍。結(jié)果，人們尋求對頻

65、率產(chǎn)生進行更好的控制，多數(shù)情況下，均是借助于頻率合成器. 這些器件利用一個給定頻率,fC來產(chǎn)生一個相關(guān)的目標(biāo)頻率（和相位）fOUT. 其一般關(guān)系可以簡單地表示為：</p><p>　　fOUT = εx× fC</p><p>　　其中，比例因子εx, 有時也被稱為歸一化頻率.</p><p>　　該等式通常利用實數(shù)逐步逼近的算法實現(xiàn)。當(dāng)比例因子為有理數(shù)時

66、，兩個相對質(zhì)數(shù)（輸出頻率和基準(zhǔn)頻率）之比將諧波相關(guān)。但在多數(shù)情況下， εx可能屬于更廣泛的實數(shù)集，逼近過程一旦處于可接受的范圍之內(nèi)即會被截斷。</p><p>　　直接數(shù)字頻率合成 頻率合成器的一種實用型實現(xiàn)方式是直接數(shù)字頻率合成 (DDFS), 通常簡稱為 直接數(shù)字合成 (DDS). 這種技術(shù)利用數(shù)字數(shù)據(jù)處理來產(chǎn)生一個頻率和相位可調(diào)的輸出，該輸出與一個固定的頻率參考或時鐘源fC.相關(guān)。在DDS架構(gòu)中，參考

67、或系統(tǒng)時鐘頻率由一個比例因子分頻來產(chǎn)生所需頻率，該比例因子由二進制調(diào)諧字可編程控制。</p><p>　　簡言之，直接數(shù)字頻率合成器將一串時鐘脈沖轉(zhuǎn)換成一個模擬波形，通常為一個正弦波、三角波或方波。如圖1所示，其主要部分為：相位累加器（產(chǎn)生輸出波形相位角度的數(shù)據(jù)）， 相數(shù)轉(zhuǎn)換器,（將上述相位數(shù)據(jù)轉(zhuǎn)換為瞬時輸出幅度數(shù)據(jù)），以及數(shù)模轉(zhuǎn)換器(DAC)（將該幅度數(shù)據(jù)轉(zhuǎn)換成采樣模擬數(shù)據(jù)點）。</p><

68、p>　　圖1.DDS系統(tǒng)的功能框圖</p><p>　　對于正弦波輸出，相數(shù)轉(zhuǎn)換器通常為一個正弦查找表（圖2）。相位累加器以N為單位計數(shù)，并根據(jù)以下等式產(chǎn)生一個相對于fC的頻率:</p><p>　　其中：M為調(diào)諧字的分辨率（24至48位）N為對應(yīng)于相位累加器輸出字最小增量相位變化的fC的脈沖數(shù)</p><p>　　圖2.典型的DDS架構(gòu)和信號路徑（帶DA

69、C）</p><p>　　由于更改N會立即改變輸出相位和頻率，因此，系統(tǒng)自身具有相位連續(xù),特點，這是許多應(yīng)用的關(guān)鍵屬性之一。無需環(huán)路建立時間，這與模擬系統(tǒng)不同，如鎖相環(huán) (PLL)。DAC通常為一個高性能電路，專門針對DDS內(nèi)核（相位累加器和相幅轉(zhuǎn)換器）而設(shè)計。多數(shù)情況下，這樣結(jié)果形成的器件（通常為單芯片）一般稱為純DDS或C-DDS。</p><p>　　實際的DDS器件一般集成多個寄存

70、器，以實現(xiàn)不同的頻率和相位調(diào)制方案。如相位寄存器，其存儲的相位內(nèi)容被加在相位累加器的輸出相位上。這樣，可以對應(yīng)于一個相位調(diào)諧字延遲輸出正弦波的相位。對于通信系統(tǒng)相位調(diào)制應(yīng)用，這非常有用。加法器電路的分辨率決定著相位調(diào)諧字的位數(shù)，因此，也決定著延遲的分辨率。</p><p>　　在單個器件上集成一個DDS引擎和一個DAC既有優(yōu)點也有缺點，但是，無論集成與否，都需要一個DAC來產(chǎn)生純度超高的高品質(zhì)模擬信號。DAC將數(shù)

71、字正弦輸出轉(zhuǎn)換為一個模擬正弦波，可能是單端，也可能是差分。一些關(guān)鍵要求是低相位噪聲、優(yōu)秀的寬帶(WB)和窄帶(NB)無雜散動態(tài)范圍 (SFDR)以及低功耗。如果是外部器件，則DAC必須足夠快以處理信號，因此，內(nèi)置并行端口的器件非常常見。</p><p>　　DDS與其他解決方案 其他產(chǎn)生頻率的方法包括模擬鎖相環(huán)(PLL),時鐘發(fā)生器和利用FPGA對DAC的輸出進行動態(tài)編程。通過考察頻譜性能和功耗，可以對這些

72、技術(shù)進行簡單的比較，表1以定性方式展示了比較結(jié)果。</p><p>　　表1.DDS與競爭技術(shù)——高級比較</p><p>　　鎖相環(huán)是一種反饋環(huán)路，其組成部分為：一個相位比較器, 一個除法器和一個壓控制振蕩器 (VCO). 相位比較器將基準(zhǔn)頻率與輸出頻率（通常是輸出頻率的N)分頻）進行比較。相位比較器產(chǎn)生的誤差電壓用于調(diào)節(jié)VCO，從而輸出頻率。當(dāng)環(huán)路建立后，輸出將在頻率和/或相位上與參考

73、頻率保持一種精確的關(guān)系。PLL長期以來一直被認為是在特定頻帶范圍內(nèi)要求高保真度和穩(wěn)定信號的低相位噪聲和高無雜散動態(tài)范圍 (SFDR) 應(yīng)用的理想選擇。</p><p>　　由于PLL無法精確、快速地調(diào)諧頻率輸出和波形，而且響應(yīng)較慢，這限制了它們對于快速跳頻和部分頻移鍵控和相移鍵控應(yīng)用的適用性。</p><p>　　其他方案，包括集成DDS引擎的現(xiàn)場可編程門陣列 (FPGAs) ——配合現(xiàn)成

74、DAC以合成輸出正弦波——雖然可以解決PLL的跳頻問題，但也存在自身的缺陷。主要系統(tǒng)缺陷包括較高的工作和接口功耗要求、成本較高、尺寸較大，而且系統(tǒng)開發(fā)人員還須考慮額外的軟件、硬件和存儲器問題。例如，利用現(xiàn)代FPGA中的DDS引擎選項，要產(chǎn)生動態(tài)范圍為60 dB的10 MHz輸出信號，需要多達72 kB的存儲器空間。另外，設(shè)計師需要接受并熟悉細微權(quán)衡和DDS內(nèi)核的架構(gòu)。</p><p>　　從實用角度來看（見表2）

75、，得益于CMOS工藝和現(xiàn)代數(shù)字設(shè)計技術(shù)的快速發(fā)展以及DAC拓撲結(jié)構(gòu)的改進，DDS技術(shù)已經(jīng)能在廣泛的應(yīng)用中實現(xiàn)前所未有的低功耗、頻譜性能和成本水平。雖然純DDS產(chǎn)品不可能在性能和設(shè)計靈活性上達到高端DAC技術(shù)與FPGA相結(jié)合的水平，但DDS在尺寸、功耗、成本和簡單性方面的優(yōu)勢使其成為許多應(yīng)用的首要選擇。</p><p>　　表2.基準(zhǔn)分析小結(jié)——頻率產(chǎn)生技術(shù)(<50 MHz)</p><p

76、>　　同時需要指出，由于DDS器件從根本上來說是用數(shù)字方法產(chǎn)生輸出波形，因此它可以簡化一些解決方案的架構(gòu)，或者為對波形進行數(shù)字化編程創(chuàng)造條件。盡管通常利用正弦波來解釋DDS的功能和工作原理，但利用現(xiàn)代DDS IC也可以輕松產(chǎn)生三角波或方波（時鐘）輸出，由此消除了前一種情況的查找表以及后一種情況的DAC的必要性，因為集成一個簡單而精確的比較器就夠了。</p><p>　　DDS的性能與限制圖像和包絡(luò)：Sin

77、(x)xx滾降 DAC的實際輸出不是連續(xù)的正弦波，而是帶有正弦時間包絡(luò)的一系列脈沖。對應(yīng)的頻譜是一系列圖像和混疊信號。圖像沿sin(x)/x 包絡(luò)分布（見圖3中的|幅度|曲線圖）。有必要進行濾波，以抑制目標(biāo)頻帶之外的頻率，但是不能抑制通帶中出現(xiàn)的高階混疊（例如，因DAC非線性所致）。</p><p>　　奈奎斯特準(zhǔn)則 要求，每個周期至少需要兩個采樣點才能重建所需輸出波形。鏡像響應(yīng)產(chǎn)生于采樣輸出頻率中 K f

78、CLOCK × fOUT. 在本例中，其中 fCLOCK = 25 25 MHz且 fOUT = 5 MHz，第一和第二鏡頻出現(xiàn)在（見圖3）fCLOCK × fOUT, o即20 MHz和30 MHz。第三和第四鏡頻出現(xiàn)在45 MHz和55 MHz。注意，sin(x)/x零值出現(xiàn)在采樣頻率的倍數(shù)處。當(dāng)fOUT 大于奈奎斯特帶寬 (1/2 fCLOCK), 時，第一鏡頻將出現(xiàn)于奈奎斯特帶寬之內(nèi)，發(fā)生混疊（例如，15 M

79、Hz的信號將向下混疊至10 MHz）。無法用傳統(tǒng)的奈奎斯特抗混疊濾波器從輸出中濾掉混疊鏡頻。</p><p>　　圖3.DDS中的Sin(x)/x滾降</p><p>　　在典型的DDS應(yīng)用中，利用一個低通濾波器來抑制輸出頻譜中鏡頻響應(yīng)的影響。為了使低通濾波器的截止頻率要求保持于合理水平，并使濾波器設(shè)計保持簡單，一種可行的做法是利用一個經(jīng)濟的低通輸出濾波器將fOUT 帶寬限制在fCLOCK

80、頻率的40%左右 。</p><p>　　任何給定鏡頻相對于基波的幅度可用sin(x)/x公式來計算。由于該函數(shù)隨頻率滾降，因此基本輸出的幅度將與輸出頻率成反比而降低；在DDS系統(tǒng)中，降低量為DC-奈奎斯特帶寬范圍的–3.92 dB。</p><p>　　第一鏡頻的幅度較大——基波的3 dB范圍內(nèi)。為了簡化DDS應(yīng)用的濾波要求，必須制定頻率計劃，并分析鏡頻和sin(x)/x幅度響應(yīng)在fOU

81、T和fCLOCK目標(biāo)頻率下的頻譜要求。輸出頻譜中的其他不需要的頻率（如DAC的積分和微分線性誤差、與DAC相關(guān)的突波能量和時鐘饋通噪聲）不會遵循sin(x)/x滾降響應(yīng)。這些不需要的頻率將以諧波和雜散能量出現(xiàn)在輸出頻譜中的許多地方——但其幅度一般會遠遠低于鏡頻響應(yīng)。DDS器件的一般本底噪聲由基板噪聲、熱噪聲效應(yīng)、接地耦合和其他信號源耦合等因素累積組合決定。DDS器件的本底噪聲、性能雜散和抖動受到電路板布局、電源質(zhì)量以及——最重要的是——

82、輸入?yún)⒖紩r鐘。</p><p>　　抖動 完美時鐘源的邊沿將以精確的時間間隔發(fā)生，而該間隔永遠都不會變化。當(dāng)然，這是不可能的；即使最好的振蕩器也是由不理想的元件構(gòu)成，具有噪聲等缺陷。優(yōu)質(zhì)的低相位噪聲晶體振蕩器的抖動為皮秒級，而且是從數(shù)百萬個時鐘邊沿累積起來的。導(dǎo)致抖動的因素有熱噪聲、振蕩器電路不穩(wěn)定以及電源、接地和輸出連接等帶來的外部干擾等，所有這些因素都會干擾振蕩器的時序特性。另外，振蕩器受外部磁場或電場

83、以及附近發(fā)射器的射頻干擾的影響。振蕩器電路中，一個簡單的放大器、反相器或緩沖器也都會給信號帶來額外的抖動。</p><p>　　因此，選擇一個抖動低、邊沿陡的穩(wěn)定的參考時鐘振蕩器是至關(guān)重要的。較高頻率的基準(zhǔn)時鐘允許較大的過采樣，而且，通過分頻可以在一定程度上減輕抖動，因為對信號進行分頻將在更長時期產(chǎn)生相同量的抖動，因而可以降低信號上的抖動的百分比。</p><p><b>　　質(zhì)

84、量的深刻影響。</b></p><p>　　噪聲——包括相位噪聲 采樣系統(tǒng)的噪聲取決于諸多因素，首要因素是參考時鐘抖動，這種抖動表現(xiàn)為基波信號上的相位噪聲。在DDS系統(tǒng)中，截斷相位寄存器輸出可能帶來因代碼而異的系統(tǒng)誤差。二進制字不會導(dǎo)致截斷誤差。但對于非二進制字，相位噪聲截斷誤差會在頻譜中產(chǎn)生雜散。雜散的頻率/幅度取決于代碼字。DAC的量化和線性誤差也會給系統(tǒng)帶來諧波噪聲。時域誤差（如欠沖/過沖

85、和代碼錯誤）都會加重輸出信號的失真。</p><p>　　應(yīng)用DDS應(yīng)用可以分為兩大類：</p><p>　　1、要求捷變頻率源以進行數(shù)據(jù)編碼和調(diào)制應(yīng)用的通信和雷達系統(tǒng)</p><p>　　2、要求通用頻率合成功能以及可編程調(diào)諧、掃描和激勵能力的測量、工業(yè)和光學(xué)應(yīng)用</p><p>　　兩種情況下，都出現(xiàn)了一種走向更高頻譜純度（更低的相位噪

86、聲和更高的無雜散動態(tài)范圍）的趨勢，同時還存在低功耗和小尺寸的要求，以適應(yīng)遠程或電池供電設(shè)備的需求。</p><p>　　調(diào)制/數(shù)據(jù)編碼和同步中的DDS DDS產(chǎn)品首先出現(xiàn)于雷達和軍事應(yīng)用之中，其部分特性的發(fā)展（性能的提升、成本和尺寸等）已使DDS技術(shù)在調(diào)制和數(shù)據(jù)編碼應(yīng)用中日漸盛行。本節(jié)將討論兩種數(shù)據(jù)編碼方案及其在DDS系統(tǒng)中的實現(xiàn)方式。</p><p>　　二進制頻移鍵控 (BFSK

87、,或簡稱FSK) 最簡單的數(shù)據(jù)編碼形式之一</p><p>　　數(shù)據(jù)的發(fā)射方式是使一個連續(xù)載波的頻率在兩個離散頻率（一為二進制1，即傳號，一為二進制0，即空號）之間變換。圖4所示為數(shù)據(jù)和發(fā)射信號之間的關(guān)系。</p><p>　　圖4.二進制FSK調(diào)制</p><p>　　二進制1和0表示為兩個不同的頻率，分別為f0和f1。這種編碼方案可以輕松在DDS器件中實現(xiàn)。代表

88、輸出頻率的DDS頻率調(diào)諧字被改變，以從將發(fā)射的1和0產(chǎn)生f0和f1。要變換輸出頻率，則須用專用的引腳FSELECT選擇含有相應(yīng)調(diào)諧字的寄存器（見圖5）。</p><p>　　圖5.利用AD9834或AD9838 DDS的調(diào)諧字選擇器實現(xiàn)FSK編碼</p><p>　　相移鍵控(PSK) 是另一種簡單的數(shù)據(jù)編碼形式。在PSK中，載波的頻率保持不變，通過改變發(fā)射信號的相位來傳遞信息?？梢岳枚?/p>

89、種方案來實現(xiàn)PSK。最簡單的方法通常稱為二進制PSK（即BPSK），只采用兩個信號相位：0°（邏輯1）和180°（邏輯0）。各位的狀態(tài)取決于前一位的狀態(tài)。如果波的相位不變，則信號狀態(tài)將保持不變（低或高）。如果波的相位改變180°，即相位反轉(zhuǎn)，則信號狀態(tài)將改變（低變?yōu)楦?，或高變?yōu)榈停?。PSK編碼可以輕松在DDS產(chǎn)品中實現(xiàn)，因為多數(shù)器件都有一個獨立的輸入寄存器（相位寄存器），可以加載相位值。該值被直接添加到載波

90、的相位，而不改變其頻率。更改該寄存器的內(nèi)容將調(diào)制載波的相位，結(jié)果產(chǎn)生一個PSK輸出。對于要求高速調(diào)制的應(yīng)用，內(nèi)置相位寄存器對的AD9834和AD9838允許其PSELECT引腳上的信號在預(yù)加載的相位寄存器之間變換，以根據(jù)需要調(diào)制載波。</p><p>　　更復(fù)雜的PSK采用四個或八個波相位。這樣，每當(dāng)相位發(fā)生變化時，二進制數(shù)據(jù)的傳輸速率將高于BPSK調(diào)制。在四相位調(diào)制 (正交 PSK),中，可能的相位角度為0&#

91、176;, +90°, ?90°, 和 +180°;每次相位變換可能代表兩個信號因子AD9830, AD9831, AD9832, 和 AD9835 提供四個相位寄存器，通過連續(xù)更新寄存器的不同相位偏移，可以實現(xiàn)復(fù)雜的相位調(diào)制方案.。</p><p>　　以同步模式利用多個DDS元件實現(xiàn)I/Q功能 許多應(yīng)用要求產(chǎn)生兩個或兩個以上具有已知相位關(guān)系的正弦波或方波信號。一個常見的例子

92、是同相和正交調(diào)制(I/Q)，在這種技術(shù)中，在0°和90°相位角度從載波頻率獲得信號信息?？梢杂孟嗤脑磿r鐘來運行兩個單獨的DDS元件，以輸出可以直接控制和操作其相位關(guān)系的信號。在圖6中，用一個基準(zhǔn)時鐘對AD9838器件編程；相同的RESET引腳用于更新兩個器件。這樣，可以實現(xiàn)簡單的I/Q調(diào)制。</p><p>　　RESET必須在上電后以及向DDS傳輸任何數(shù)據(jù)之前初始化。結(jié)果可將DDS輸出置于

93、已知相位，使其成為共同的參考角度，以便同步多個DDS器件。當(dāng)新數(shù)據(jù)被同時送至多個DDS器件時，DDS之間可以保持相關(guān)相位關(guān)系，或者通過相位偏移寄存器可以預(yù)測性調(diào)整多個DDS之間的相對相位偏移。AD983x系列DDS產(chǎn)品擁有12位相位分辨率，有效分辨率為0.1°。</p><p>　　圖6.同步兩個DDS元件</p><p>　　作者：Brendan Cronin[brendan.

94、cronin@analog.com]是ADI核心產(chǎn)品和技術(shù)(CPT)部門的一位產(chǎn)品營銷工程師。Brendan于1998年加盟ADI，在工業(yè)和汽車產(chǎn)品部門工作了六年，擔(dān)任混合信號設(shè)計工程師。Brendan目前主要研究線性和相關(guān)技術(shù)。</p><p><b>　　外文文獻原文2：</b></p><p>　　Ask The Application Engineer—33

95、All About Direct Digital Synthesis</p><p>　　By Eva Murphy, (eva.murphy@analog.com)Colm Slattery (colm.slattery@analog.com)</p><p>　　By Analog Dialogue Volume 38 Number 3 of ADI</p><

96、p>　　What is Direct Digital Synthesis?Direct digital synthesis (DDS) is a method of producing an analog waveform—usually a sine wave—by generating a time-varying signal in digital form and then performing a digital-to

97、-analog conversion. Because operations within a DDS device are primarily digital, it can offer fast switching between output frequencies, fine frequency resolution, and operation over a broad spectrum of frequencies. Wit

98、h advances in design and process technology, today’s DDS devices ar</p><p>　　Why would one use a direct digital synthesizer (DDS)? Aren’t there other methods for easily generating frequencies?The ability to

99、 accurately produce and control waveforms of various frequencies and profiles has become a key requirement common to a number of industries. Whether providing agile sources of low-phase-noise variable-frequencies with go

100、od spurious performance for communications, or simply generating a frequency stimulus in industrial or biomedical test equipment applications, conveni</p><p>　　Many possibilities for frequency generation are

101、 open to a designer, ranging from phase-locked-loop (PLL)-based techniques for very high-frequency synthesis, to dynamic programming of digital-to-analog converter (DAC) outputs to generate arbitrary waveforms at lower f

102、requencies. But the DDS technique is rapidly gaining acceptance for solving frequency- (or waveform) generation requirements in both communications and industrial applications because single-chip IC devices can generate