電氣工程及其自動化外文文獻(xiàn)翻譯 一種使用單片異步微控制器的新型非接觸式智能ic卡

1、<p>　　3250單詞，17800英文字符，中文4600字</p><p>　　出處：Abrial A, Bouvier J, Renaudin M, et al. A new contactless smart card IC using an on-chip antenna and an asynchronous microcontroller[J]. IEEE Journal of Solid-

2、State Circuits, 2000, 36(7):1101-1107. </p><p>　　A new contactless smart card IC using an on-chip antenna and an asynchronous microcontroller</p><p>　　A Abrial ， J Bouvier ， 

3、M Renaudin ， P Senn</p><p>　　Abstract—This paper describes a new generation of Contactless Smart Card Chip which integrates an on-chip coil connected to a power reception system and an emitter/rece

4、iver module compatible with the IS0 14443 standard, together with an asynchronous quasi-delay insensitive (QDI) 8-bit microcontroller. Beyond the Contactless Smart Card application field, this new chip demonstrates that

5、system-on-chip integrating power reception and management, radio-frequency communication, and signal processing </p><p>　　Index Terms—Asynchronous processor, coil-on-chip, quasi-delay insensitive circuits, S

6、mart Cards, system-on-chip.</p><p>　　I. INTRODUCTION</p><p>　　THE Smart Card market enters a new era, with a booming number of applications in various domains and new countries willing to use th

7、is technology. </p><p>　　Smart Cards are becoming more and more ubiquitous and the trend is to integrate a card reader in all kind of equipment (PCs,PDAs, mobile phones, etc.). E-commerce, citizen administra

8、tion, and others could be, through the Internet, good vehicles to allow service providers to develop new services using the Smart Card as a high-security key element. </p><p>　　In this context, contactless S

9、mart Cards should play an important part. The absence of contact induces lower maintenance cost, improves ease of use, reliability, and, therefore, end-user satisfaction. They are declined in several types according to t

10、he location of the antenna. It can be on the card, on the module, or integrated directly on the chip. This later technique significantly decreases card fabrication cost. Moreover, as the user still inserts his card in a

11、reader slot, transactions rema</p><p>　　These main key technologies used to design this new Smart Card chip are presented in Section II. The Smart Card chip design is detailed in Section III, and the design

12、methodology is briefly described in Section IV. Experimental results are given in Section V.</p><p>　　II. INNOVATION</p><p>　　The innovation of this chip lies in the association on the same die

13、of two key technologies : an integrated power reception system with an on-chip coil , and an 8-bit CISC QDI asynchronous microcontroller . This association enables us to take advantage of the asynchronous logic propertie

14、s in order to decrease the design constraints of the integrated power reception system and also to increase the working domain of the digital processing part.</p><p>　　In fact, the asynchronous logic has thr

15、ee interesting advantages valuable for the Contactless Smart Card application considered here. Instead of being clock driven, asynchronous circuits are data driven which results in a lower mean-power consumption. Instead

16、 of implementing a central control unit, asynchronous circuits implement a distributed control system which results in smaller current peaks and then lower electromagnetic emission because the electrical activity is spre

17、ad over time. Finally</p><p>　　Since the QDI 8-bit microcontroller is so robust with respect to the power supply variations (see Section III), the design of the power reception system is made easier: lower a

18、verage power delivered, as well as the peak power, and simplified regulation of the supply voltage. This not only makes the design easier, but also decreases the area (smaller VDD smoothing capacitance).Finally, because

19、of its low current peaks the QDI asynchronous microcontroller does not interfere with the load modulatio</p><p>　　III. SMART CARD CHIP DESIGN </p><p>　　The Smart Card chip is composed of four ma

20、in blocks (Fig. 1). The RF front-end recovers power from the integrated antenna, which forms a transformer with the external read</p><p>　　antenna. The recovered power is then stabilized and supplies the who

21、le chip: the asynchronous microcontroller and a synchronous dedicated interface between the RF block and the asynchronous circuit.</p><p>　　This interface is driven by a reception-enable signal (REN) control

22、led by the microcontroller. In reception mode, the RF interface demodulates data sent by the reader. In emission mode, data are sent to the reader using a load modulation. The system is ISO14443-B compliant .</p>

23、<p>　　When the Smart Card is inserted in the reader slot, as soon as the stabilized supply reaches a sufficient level, reset is activated by the RF interface. The microcontroller executes the boot program contained

24、in ROM and then waits for data coming from the reader. The communication between the reader and the Smart Card is functionally asynchronous. The combination of the REN signal and the start and stop bits (the communicatio

25、n between the reader and the chip is made on an asynchronous mode, with</p><p>　　start and stop bits), encapsulating the transmitted byte implements a half-duplex communication.</p><p>　　A. Anal

26、og Block Design</p><p>　　Since there are no contacts, power and data are recovered from RF signals emitted by the reader. The analog block is in charge of</p><p>　　1) powering the chip;</p>

27、;<p>　　2) demodulating/modulating data from/to the reader;</p><p>　　3) recovering the clock used in the synchronous/asynchronous interface.</p><p>　　Compared to other contactless technolo

28、gies , the card is inserted in a slot which ensures that the distance chip reader is kept constant and small: the variations in distance are within millimeters. This enables the integration of the coil on-chip. Then, the

29、re is no need for the voltage which is recovered from the RF power to be very well regulated, as it is the case for contactless cards which operate on a “touch and go basis.” The design of the power management and analog

30、 block circuitry is ac</p><p>　　The block diagram of the RF front-end is described in Fig. 2.It is built of the following parts.</p><p>　　The full wave rectifier (FWR) is a bridge composed of n

31、MOS and p MOS transistors. The electro-motive-force (EMF) induced in the on-chip antenna is applied to the FWR inputs. The negative output is connected to the</p><p>　　bulk and the positive output is connect

32、ed to a 500 Pf smoothing capacitor. It delivers the non regulated voltage</p><p>　　NRV to the chip.</p><p>　　2) The clock recovery block extracts the 13.56-MHz clock from the RF carrier signal.

33、For this purpose, the input of a Schmidt trigger is connected to one of the two antenna terminals.</p><p>　　3) The power-on detector. This block is composed of a voltage reference, a differential comparator

34、and filters to reject modulation parasitics. It triggers a RESET when the NRV reaches a given level.</p><p>　　4) The data demodulator is based on NRV amplitude transitions due to NRZ coded transmission from

35、reader to chip. The data demodulator extracts the data mixed with NRV ,by detecting negative and positive transitions. The two outputs drive the inputs of an RS latch which makes the data available to the interface.</

36、p><p>　　5) The load modulator is built of a resistor (Rmod, see Fig. 3)switched by an n MOS transistor controlled by the data to be sent to the reader. It induces an amplitude modulation in the inductor antenna

37、. In emission, the modulator has to modulate the power absorbed by the chip at an 847-kHz BPSK rhythm. This is made by a modulation of I(NRV),. This induces an EMF in the reader solenoid. The EMF value is where is the mu

38、tual inductor and the carrier frequency.</p><p>　　6) The current generator is associated with a zener diode to achieve power regulation. As we want information to be transmitted to the reader when the microc

39、ontroller is running, and since a load modulation is used, care must be taken to the dynamic current consumption of the microcontroller which can induce NRV current variations and then corrupt the communication. To preve

40、nt this phenomena from occurring, a constant current source is used to feed the logic together with a 2-V shunt voltage sta</p><p>　　In this prototype, the current generator is designed to deliver 15 mA in o

41、rder to supply the microcontroller as well as an external nonvolatile memory included in a demonstrator under development.</p><p>　　B. Synchronous/Asynchronous Interface </p><p>　　The block diag

42、ram of the interface is presented in Fig. 5. It is composed of a divider, a BPSK modulator and a block which formats the data coming from the external reader and from the microcontroller. </p><p>　　The RF 13

43、.56-MHz carrier is recovered and divided to provide a 847-kHz signal used to clock the interface. On the RF interface side, bytes are encapsulated with start and stop bits which are then received or emitted sequentially

44、at the 847-kHz bit rate. On the microcontroller side, an asynchronous four-phase bundle-data protocol is used (8-bit data, request and acknowledge signals) to control data exchange asserting P5ack. The four-phase handsh

45、ake protocol then completes with two return-to-zero</p><p>　　The handshake protocol ensures that both the microcontroller and the interface are available to accept and transmit a byte in emission or receptio

46、n. Thus, the microcontroller will be idled as long as the interface does not grant its request. The program execution will resume when the data byte is finally sent or received. A one-byte buffer allows the microcontroll

47、er and the interface to run concurrently. Failure may only occur in reception if the microcontroller does not read the incoming byte i</p><p>　　C. QDI Asynchronous 8-bit Microcontroller</p><p>　

48、　The QDI asynchronous 8-bit microcontroller is a CISC machine, based on a dedicated “l(fā)uxurious” microarchitecture (Fig. 6). In order to facilitate the design of a “C” compiler and also to limit memory accesses, we decide

49、d to integrate two different register-files: eight 8-bit registers are devoted to data, and eight 16-bit registers are devoted to pointers (including the program counter and the stack pointer). Specific arithmetic units

50、 are associated with each register files enabling concurrent </p><p>　　The ROM includes a Built-In-Self-Test (BIST) program which is executed at reset according to the boot mode selected (eight modes are ava

51、ilable). It is a 350 assembly instruction routine which performs a stuck-at-fault test which computes a signature written, on the fly, on one of the parallel port to report on self-test progress. The QDI asynchronous log

52、ic used is self-testable because a stuck-at fault on any input of any gate will cause a handshake to stop for ever (no “premature firing” ). As </p><p>　　? Instruction set</p><p>　　The eight 8-b

53、it data registers are named r0 to r7, and the eight 16-bit index registers i0 to i7, where i6 and i7 are the stack-pointer and the program-counter respectively. The controller implements the common arithmetic and logic i

54、nstructions. All instructions are encoded within one word (16 bits). Four basic addressing modes are available (immediate, register, indexed with displacement, indexed post-incremented or pre-decremented) which can be us

55、ed in conjunction with data or index register o</p><p>　　? Architecture design</p><p>　　The microcontroller core is designed using the so-called quasi-delay insensitive (QDI) logic . A four-phas

56、e protocol is used in conjunction with an n-rail encoding. This microcontroller, named MICA, has been a vector for developing new skills in the design of standard-cell based QDI asynchronous circuits. The design of MICA

57、was focused on two correlated concerns: designing distributed asynchronous finite state machine and designing for low power.</p><p>　　In order to reduce the power consumption of the microcontroller we have w

58、orked on minimizing the number and the energy cost of communication actions occurring during the execution of each instruction, and minimizing the number of sequential steps to perform each instruction. In other words, i

59、nstead of designing the architecture around a large central sequencer, we have tried to distribute the sequencing implementation all over the architecture as much as possible. The asynchronous logic is parti</p>&

60、lt;p>　　Thus, the architecture of MICA has been designed as a distributed system, each part providing specific services. For example, the two register-files, the status register and the memory integrate local units whi

61、ch manage the memory resources. These modules implement functions such as “read,” “write,” “read then write back,” or even more complex function vlike: read a byte, increment/decrement the pointer/address, and read the c

62、orresponding byte (Cp and Pl instructions for examples use these featu</p><p>　　using a low-power data encoding. Instead of using dual-rail coding, we have implemented n-rail coding (also called “One Hot”),

63、i.e., one out of the N wires is active during a transaction (instead of one out of two with dual-rail). The different parts of the architecture are all controlled by the main sequencer through channels using 5-rail to 12

64、-rail data encoding which minimizes the number of transitions per communication action, and hence minimizes the dynamic power consumption. The data paths</p><p>　　? Microcontroller performance</p><

65、;p>　　Before integrating the microcontroller in the Smart Card chip, a test chip has been designed, fabricated and tested. The microcontroller has been easily tested thanks to the BIST, and was fully functional at firs

66、t silicon between 3 V down to 0.8 V (2.5 V is the nominal voltage of the 0.25- m CMOS technology used). Table II gives the MIPS (mean number of instructions executed per second when running the BIST program), Power and M

67、IPS/Watt figures at different voltages (based on the total current c</p><p>　　IV. DESIGN METHODOLOGY</p><p>　　The Smart Card chip represents a complex system on chip with several different desig

68、n styles. The analog has been designed in full custom. The synchronous/asynchronous interface between the analog block and the microcontroller has been modeled using VHDL as a synchronous finite state machine and synthes

69、ized with standard CAD tools. As regards to the </p><p>　　asynchronous logic, the microcontroller was first described in CHP [1], a high-level language well suited to model asynchronous circuits. The model w

70、as then refined to ob-tain the final distributed architecture. Model validation was performed by VHDL simulation, thanks to a CHP to VHDL translator. The synthesis of the CHP model into QDI logic was performed by hand an

71、d the schematic manually captured in a standard design framework. The microcontroller is thus built of 1) founder standard cells pl</p><p>　　V. EXPERIMENTAL RESULTS</p><p>　　The chip was fabrica

72、ted at the STMicroelectronics Crolles plant using a 6 metal-layer 0.25- m CMOS process. Pads are included in this first prototype in order to test the chip and perform measurements on both the digital and analog parts. T

73、he total chip area is 16 mm including these pads. The on-chip-coil is surrounding the chip (Fig. 8). The coil is made of six turns implemented with the upper five metal layers. Its area is 1.5 mm .The CISC microcontrolle

74、r with its memory represents one million</p><p>　　For validating the chip in a system environment, a reader connected to a PC via an RS232 port was designed. The reader includes the RF oscillator, the 10% AS

75、K modulator, the BPSK detector, and provides 1W under 6-V conditions. The chip was integrated on a prototype card. When inserting the card into the reader magnetic field (11 gauss, with load), a program is downloaded int

76、o the microcontroler RAM and data are exchanged between the external PC and the card. The circuit has been successfully val</p><p>　　VI. CONCLUSION</p><p>　　The chip presented in this paper is t

77、he first prototype that fully integrates a Contactless Smart Card (antenna, power reception, RF communication and digital processing). It demonstrates that the design of such System-On-Chip is feasible using the latest i

78、ndustrial technologies. Future investigations will focus on the benefits of the use of an asynchronous microcontroller with respect to area gain (VDD smoothing capacitor), design complexity reduction and software simplif

79、ication. </p><p>　　Another very interesting and promising perspective is to investigate the ability of asynchronous circuits to improve Smart Card circuits resistance against well known attacks such as DPA a

80、nalysis, fault and glitch attacks .</p><p>　　一種使用單片異步微控制器的新型非接觸式智能IC卡</p><p><b>　　摘要 </b></p><p>　　本文介紹了一種新的非接觸式智能卡芯片，它集成了一個片上線圈，連接到電源接收系統(tǒng)和發(fā)射器/接收器與ISO 14443標(biāo)準(zhǔn)兼容的模塊，連同一個異

81、步準(zhǔn)延遲不敏感（QDI）的8位微控制器。除了非接觸式智能卡應(yīng)用領(lǐng)域，這個新的芯片表明，系統(tǒng)芯片上集成的電源接收和管理，射頻通信，信號處理是可行的。它綜合了模擬/數(shù)字以及同步/異步邏輯器件，并安裝了一個意法半導(dǎo)體公司的0.25微米、CMOS六金屬層的半導(dǎo)體。</p><p>　　索引詞 異步處理器，片上線圈，異步準(zhǔn)延遲不敏感，智能卡，系統(tǒng)芯片。</p><p><b>　　I 介

82、紹</b></p><p>　　隨著智能卡在不同領(lǐng)域應(yīng)用的迅速發(fā)展，智能卡市場進(jìn)入了一個新的時代，更多國家將應(yīng)用這項(xiàng)技術(shù)。</p><p>　　智能卡現(xiàn)在越來越普及，并且都趨向于在各種設(shè)備上集成讀卡器，例如PC，PDA,移動電話，等等。使用智能卡，商家、城市行政部門和其它的服務(wù)商可以通過網(wǎng)絡(luò)提供高安全性的新型服務(wù)。</p><p>　　非接觸式智能卡將要

83、在這些應(yīng)用中起重要作用。讀寫時不用進(jìn)行接觸不僅縮減了維修費(fèi)用，而且提高了卡的易用性和可靠性，贏得了最終用戶的滿意。它通過本地的天線拒絕了幾項(xiàng)服務(wù)。它可以應(yīng)用在卡上，應(yīng)用在模塊上，或直接集成到芯片上。這項(xiàng)技術(shù)意味著卡的制造費(fèi)用將減少。而且使用者一直將卡插在讀卡器里，系統(tǒng)仍然是安全的。因?yàn)榇蠖鄶?shù)應(yīng)用系統(tǒng)成本低、低功耗。這項(xiàng)工程的總目標(biāo)是整合射頻線圈，符合ISO14443頻率發(fā)射器/接收器與一個異步微控制器。將整個系統(tǒng)集成到半導(dǎo)體硅上降低制造

84、成本和使非接觸式智能卡更加可靠。</p><p>　　用于設(shè)計新型非接觸智能卡的主要技術(shù)將在第二部分有所陳述。智能卡設(shè)計細(xì)節(jié)在第三部分陳述，設(shè)計的方法論主要在第四部分講述。實(shí)驗(yàn)結(jié)果在第五部分給出。</p><p><b>　　II．創(chuàng)新</b></p><p>　　本集成電路的創(chuàng)新歸功于兩項(xiàng)關(guān)鍵技術(shù)，集成在芯片上的電能接收線圈和一個8位CISC

85、 QDI異步處理器。這些聯(lián)合是我們在異步邏輯上的寶貴財富。以便于降低綜合功耗接收系統(tǒng)的限制并且工作范圍擴(kuò)展到數(shù)字信號處理領(lǐng)域。 </p><p>　　事實(shí)上，異步邏輯對于非接觸式智能卡應(yīng)用有三方面的意義。使用平均功耗較低的異步電路數(shù)字驅(qū)動代替了時鐘驅(qū)動。使用小峰值電流的異步電路分布式控制系統(tǒng)代替中央控制執(zhí)行單元，且減少了電磁輻射。最后使用自我調(diào)節(jié)的異步電路來控制時間代替了同步定時器。因此QDI異步電路對電壓變化并

86、不敏感，并且在所接到的信號的最大速度上運(yùn)行。</p><p>　　8位QDI微處理器電能供應(yīng)系統(tǒng)的成熟（見第三部分），使得功耗接收系統(tǒng)的設(shè)計變得容易。較低的平均電力傳輸，相同的最大功耗，以及簡化了的電壓提供規(guī)則。這些不只是使設(shè)計變得容易也減少了面積（較少的VDD濾波電容）。最后因?yàn)樗牡碗妷悍逯?，QDI異步微控制器不會干擾符合ISO14443標(biāo)準(zhǔn)的IC卡和讀卡器之間的通信調(diào)制。這使得當(dāng)芯片傳輸數(shù)據(jù)到讀卡器時微控制

87、器仍能運(yùn)行，這減少了軟件的復(fù)雜性和對存儲器空間的需求。</p><p>　　III．智能卡芯片設(shè)計</p><p>　　智能卡芯片由四部分組成（如圖1）。</p><p>　　通過變壓互感器來提供能量的射頻天線以及接受芯片上的能量接收窗口，能夠穩(wěn)定為整個芯片提供能量；異步微控制器和一個RF模塊與異步電路專用同步接口。</p><p>　　這個

88、接口由微處理器接收到的許可信號驅(qū)動。在接收模式中，RF接口解調(diào)數(shù)據(jù)通過讀卡器發(fā)送。在發(fā)射模式中，數(shù)據(jù)使用負(fù)載調(diào)制送入讀卡器。系統(tǒng)符合ISO14443-B標(biāo)準(zhǔn)。</p><p>　　當(dāng)智能卡插入讀卡器插槽時，一旦電源供應(yīng)達(dá)到穩(wěn)定，RF接口被復(fù)位為活動狀態(tài)。微控制器執(zhí)行固化在ROM中的啟動程序，然后等待從讀卡器傳來信號。在解讀器和智能卡之間的信息傳遞是異步的。信號傳遞的開始與結(jié)束位（讀卡器和集成電路之間的信息交流被設(shè)

89、定為異步方式）半雙工通信模式傳遞封包字節(jié)。</p><p><b>　　A 模擬電路設(shè)計</b></p><p>　　由于沒有接觸，能量和數(shù)字信號都通過脈沖頻率被讀卡器接收。</p><p><b>　　模擬電路的功能：</b></p><p>　?。?）為集成電路提供電源</p>&

90、lt;p>　?。?）從讀卡器調(diào)制/解調(diào)數(shù)據(jù)</p><p>　　（3）恢復(fù)時鐘用于同步或異步接口</p><p>　　與其它的不接觸工藝相比，卡片插入插槽保持的距離在毫米之內(nèi)，這使電路集成在一塊芯片上成為可能。由于使用RF射頻提供能量而不需要電壓，電源設(shè)計和模擬模塊的電路圖也相應(yīng)的得到簡化。RF模塊如圖2所示。</p><p>　　它由以下幾部分組成：<

91、/p><p>　　1全波整流器由nMOS和pMOS組成的晶體管橋接而成，天線集成電動勢用于整流器輸入，負(fù)載輸出連接到大部分，正向輸出連接到500PF濾波電容。</p><p>　　2時鐘恢復(fù)模塊提供13.56MHZ時鐘頻率從RF獲得載波信號。為了實(shí)現(xiàn)這個效果輸入連接到一個或兩個天線終結(jié)點(diǎn)。</p><p>　　3電源監(jiān)測器。這個模塊由一個參考電壓，一個微檢測儀和過濾器組

92、成。當(dāng)NRV 打到給定的電平時它觸發(fā)一個復(fù)位信號。</p><p>　　4數(shù)字解調(diào)基于NRV振幅，由NRZ編碼傳遞到讀卡器芯片。數(shù)據(jù)解調(diào)器選錄數(shù)據(jù)并且探測出是正向還是反向傳遞。兩個輸出驅(qū)動RS鎖存輸入，使得數(shù)據(jù)可以被接口訪問。</p><p>　　5負(fù)載調(diào)節(jié)器由一個NMOS晶體管構(gòu)成的電阻開關(guān)（如圖3）控制數(shù)據(jù)發(fā)送到讀卡器上。它導(dǎo)致感應(yīng)天線的振幅調(diào)制。當(dāng)發(fā)射時，芯片使調(diào)節(jié)器調(diào)節(jié)電源工作在8

93、47KHZ BPSK。這在譯讀器中引起螺形電動勢，電動勢值由突變和夾帶頻率決定。EMF值是</p><p>　　電流發(fā)生器和齊納二極管完成功耗調(diào)節(jié)。我們需要信息在微控制器運(yùn)行時傳遞，因此，需要一個下載調(diào)制器，必須重視的是微控制器消耗原動電流，破壞信息。為了防止這種現(xiàn)象發(fā)生用一個不間斷電流源提供一個穩(wěn)定的2V電壓。持續(xù)電流發(fā)生器被用于供應(yīng)邏輯部分需要的最大電流，這個裝置確保了一個不變的NRV電流?？梢杂绍浖?zhí)行消除

94、負(fù)載調(diào)制產(chǎn)生的雜波。（如圖4）</p><p>　　在這個裝置中，電流發(fā)生器被設(shè)計輸出15MA電流以便滿足控制器和外部非易失性存儲器的需要。</p><p>　　B 同步/ 異步接口</p><p>　　接口模塊簡圖如圖5所示，它由一個分壓器、一個解調(diào)器和一個處理來自外部讀卡器和微控制器數(shù)據(jù)格式模塊組成。</p><p>　　這個13.56-

95、MHZ的RF的頻率讀入器，被覆蓋并分開提供一個847KHZ的接口時鐘信號。在RF接口一側(cè)，數(shù)據(jù)被以847KHZ的頻率發(fā)射接受。在微控制器一側(cè)，采用異步的四相位數(shù)據(jù)包協(xié)議（8位數(shù)據(jù)，請求和應(yīng)答信號），用于控制QDI異步微控制器的數(shù)據(jù)傳輸。</p><p>　　這個接口執(zhí)行兩種轉(zhuǎn)變：協(xié)議轉(zhuǎn)變和連續(xù)/并行或平行/連續(xù)之間的轉(zhuǎn)變。它被設(shè)置成一個異步有限狀態(tài)的機(jī)器，假定抽樣異步控制信號是象P5rep和P4ack一樣的。當(dāng)有

96、數(shù)據(jù)從卡讀入時，微控制器禁止請求由P5rep信號控制的寫入接口信號。當(dāng)字節(jié)緩沖器無內(nèi)容時，四相信號交換協(xié)議完成兩個返0相位。當(dāng)從讀卡器接收數(shù)據(jù)時，REN信號被置為高電平，微控制器準(zhǔn)備響應(yīng)P4ack信號，接收一個輸入字節(jié)。當(dāng)接收器接收到一個有效的數(shù)據(jù)時，接口應(yīng)答上升的P4req信號。歸零的握手相位完成。</p><p>　　握手協(xié)議確保微控制器和接口都能有效的傳送和接收數(shù)據(jù)。因此，只要在接口沒有授權(quán)微控制器的請求時

97、，微控制器將保持空閑。當(dāng)有數(shù)據(jù)再次傳送或者接收時，程序?qū)⒃俅螆?zhí)行。1字節(jié)的數(shù)據(jù)緩沖器使微控制器和接口能正確運(yùn)行。當(dāng)微控制器沒有及時讀取輸入數(shù)據(jù)時才會產(chǎn)生錯誤，在這種情況下接口將重寫未讀的比特。這種信息交流失敗可以用軟件校錯改變。</p><p>　　C QDI 8位異步微控制器</p><p>　　QDI 8位異步微控制器是一個采用CSIC指令集的微型處理器。（如圖6）</p>

98、<p>　　為了使C語言編譯簡單和限制記憶體訪問，我們決定綜合兩個不同的寄存器文件，一個是8位寄存器用于存儲數(shù)據(jù)，一個是16位寄存器用于指針（包括程序計數(shù)器和堆棧指針）。特殊算術(shù)單元聯(lián)合每個寄存器單元，允許并發(fā)的數(shù)據(jù)計算和尋址。一個專門的單元用于管理Z,N,V狀態(tài)位,外部單元也包括在內(nèi)，支持六個8位的并行接口（一個輸入，四個輸出，一個雙向控制可擦寫存儲器以及同步 /異步接口），還支持四個串行連接（使用兩個延遲協(xié)議協(xié)調(diào)高性能

99、RISC異步處理器）。此外，微處理器集成了16KB的RAM和2KB的ROM。</p><p>　　ROM包含一個自測試程序，當(dāng)系統(tǒng)復(fù)位時依照啟動模式執(zhí)行（八種模式可以使用）。它是一個350匯編指令程序，用以完成故障測試，確定信號寫入，在并行端口匯報運(yùn)行結(jié)果。QDI異步邏輯模塊使用自測試，因?yàn)槿魏伍T的輸入故障將使得握手停止。（不是過早開通）。結(jié)果，BIST程序?qū)牟划a(chǎn)生完整的信號。</p><p

100、><b>　　命令設(shè)置</b></p><p>　　8位數(shù)據(jù)寄存器命名為RO到R7，16位索引寄存器命名為i0到i7。I6和I7分別為堆棧指針和程序計數(shù)器?？刂破鳛槠胀ǖ乃阈g(shù)和邏輯操作，所有的操作都是一個字節(jié)的編碼。四種基本尋址模式可用（直接的，寄存器，位移索引，增量/減量索引）于數(shù)據(jù)或者索引寄存器的與運(yùn)算操作數(shù)。最后控制器裝置的中斷裝置等待中斷命令。表1總結(jié)了指令集合，注解了COPY