serdes introduction

1、SERDES Introduction,,Agenda,I/O OverviewSERDES & CDR FundamentalSERDES MeasurementsHow to Evaluate a SERDES Device?High Speed Design Consideration,I/O Overview,Data transmission, is a means of moving data from on

2、e location to another. There are two main parameters that define how the information is transferred. Distance, the space between the sending and the receiving systems speed, the rate at which data has to be passed to

3、the receiving deviceAs Cable length increases, the speed at which the information is transmitted must be lowered in order to keep the bit error rate down,,I/O Types,I/O CELL “Single Ended”,,,I/O Cell “Differenti

4、al”,,,,,,,,,,,,,,,,,2 to 5 volt swing,100 to 900mV swing,I/O Interfaces,,,,,,Source-Synchronous,single-ended,Source-Synchronous,differential,Clock and DataRecovery,differential,Interface“style”,Data rate(per pin)

5、,,,,,1Gbit/s,2Gbit/s,3Gbit/s,4Gbit/s,,,Conventional,single-ended,Conventional,differential,,,,,PCI, AGP-1X,PCI-X, AGP-2X,SDR, ZBT, SyncBurst,General system logic,LVDS,CSIX,DDR, QDR,RapidIO,HyperTransport,InfiniBand,XAU

6、I,8b/10b Encoded LVDS,n-LVDS,,,,,,,,,,,,,,,UTOPIA-4,,POS-PHY L4,I/O Timeline,Number of Standards Has Increased Dramatically,,Agenda,I/O OverviewSERDES & CDR FundamentalSERDES MeasurementsHow to Evaluate a SERDES D

7、evice?High Speed Design Consideration,Parallel vs. Serial Data Transfer,Parallel data transferMultiple lines consume board spaceLines interfere with each otherEach line needs its own termination circuitrySerial Data

8、 TransferFewer lines yields reduced board spaceLine interference can be minimizedUses a fraction of the termination circuitry vs. parallelNo Skew Issues,,,,,,,,,,,,,,,,,,,,Backplane,,,,,Backplane,A SERDES provides a

9、means to convert a wide parallel data bus to an equivalent bandwidth Single ‘wire’ serial stream,Parallel,Parallel,Serial,Serial,Why SERDES?,At Very High Speeds, Board-Level Parallel Data Becomes Nearly Impossible to Ma

10、nageVariances in Trace Characteristics and Lengths Contribute to Skew:Data to Data SkewClock to Data SkewTrace count and crosstalkBackplane Cost is proportional to traces and skew requirementsLogic is Best Performe

11、d on Parallel DataA SERDES Allows the Best of Both WorldsSerial Data with an Embedded Clock for Distributing Across BackplanesParallel Data with Separate Clock for Logic Manipulation,,Logic,,,,,,,,,,,,,,,,,FromBackpl

12、ane,ToBackplane,,,,,,,,,SERDES,,,CLK,,,CLK,SERDES Functionality,A SERDES has a: Transmit section (SERializer) and a Receive section (DESerializer), also know as a CDRThe transmit portion integrates:DATA with aCLOCK

13、 signal to modulate the clock pulse (Similar to Manchester encoding),CLK,SERDES,,,,,,,,,,,,,Data 9:0 @ 100 MHz,Embedded Clock and Serial Data @ 1 Gbps,100 MHz,11 Traces Vs 1 (actually 1 pair of traces),CDR Functionalit

14、y,The receive portion (CDR) finds both theunderlying clock and thestream of data from this modulated clock signal. This is known as:“Clock and Data Recovery (CDR)”,PLL,PHASEGEN,,,Pll clk,,,Phase 7 clk,Phase 0 clk,Ph

15、ase 1 clk,Phase 2 clk,VALID CHARACTER DETECT,,,,SERIAL BIT STREAM,,RCV BYTE CLK,,DATA CHARACTER,-All 8 phases of the pll clk sample the serial stream-Some of the phases will sync to the data stream (I.e. valid charact

16、er is detected)-clk in the middle of the group of phases that detect valid characters is selected as the RBC,,,,SERIAL BIT STREAM,CDR Functionality….,Next, The Deserializer de-muxes the serial data to the original 10-b

17、it data stream,CDR(Deserializer),,,,,,,,,,,Data 9:0 @ 100 MHz,,,Recovered Clock (RBC):100 Mhz,SERDES & CDR Continued….,SERDES Benefits Include:Extends the reach at high speedsClock & Data are now prone to id

18、entical skew which is manageable and more easily recoveredReduces the overall number of traces on the backplane by ~10xSignificantly Reduces the overall pins per device by ~10x,CDRs and 1’s Density…,The CDR’s PLL must

19、lock onto the embedded clock in the serial streamThis requires a minimum number of 1/0/1 transitions per unit timeA normal data stream however, cannot guarantee a minimum number of transitions….We need to somehow man

20、age this…..This is accomplished usually by 1 of 2 methods:Encoders/Decoders (8B/10B for Ethernet) orScramblers/Descramblers (for SONET),8B10B Encoding/Decoding,Encoding EnsuresProper Transitions toRecover the Clock,

21、Output is 10 bits worth of data, however there is only 8 bits worth of meaningful data,,DC Balancing,Another Issue for the PLL is DC Shift/Balancing…A given data stream may have a higher percentage of 1s or 0s over a gi

22、ven time period. This is called running disparity, which is a measurement of whether the encoded patterns are leaning toward too many ones ( RD+ or positive disparity) or too many zeroes (RD- or negative dispari

23、ty).‘DC Balancing’ is a method to null or eliminate this DC- bias and is part of the 8B10B coding scheme.The 8B10B encoder selects one of the two possible codes for each datum based on the current state of the disparit

24、y (RD+ / RD-).One code has a higher percentage of 1s to add positive biasThe other code has a higher percentage of 0s to add negative bias,8B10B Encoding/Decoding Summary…,Converts 8-Bits of Data into a 10-Bit CodeNo

25、More Than Five 1’s or 0’s Can be Consecutively TransmittedForces Data Transitions Such That an Embedded Clock is RecoverableApplicationsGigabit Ethernet10Gigabit Ethernet Fibre Channel8B10B encoding translates to a

26、 25% bandwidth overhead,SONET Scrambling,What is Scrambling and Why is it used?Ensures Ample Transitioning for Clock RecoverySONET scrambling is defined as X7+X6+1: No overheadCertain overhead bytes not scrambledCo

27、uld be implemented as:,,Stream of 127 bytes,8 bit Result,,XOR,,,(X^^7),(X^^6),FIFO Alignment,Typically, a SERDES data stream may run at a 3.125 Gbps rateA Designer may, however require a 6.25 Gbps or higher bandwidthTh

28、e designer can chose to Bind 2 or more channels to achieve the higher rateThe Binding of the channels requires that the two SERDES channels be aligned after reception since at 3.125Gbps, 2” of skew corresponds to a Full

29、 Signal of delay (1 bit)A complete SERDES incorporate Multi-channel FIFO alignment and recognition of Comma Characters to achieve the alignment,,Channel 1,Channel 2,Binding these two channels requires recognition of the

30、 alignment point and FIFOs to store and align the data,,Receive data Alignment W/8b/10b Decoding,,7,0,WordP,,7,0,WordQ,,7,0,WordR,,7,0,WordS,0,7,17,27,37,MRWDx(39:0),,,,,,DeMUXBLOCK,,,7,0,,8,Word

31、S,,7,0,,8,WordR,,7,0,,8,WordQ,,7,0,,8,WordP,SRDBx(7:0),RCOMMAx(3),RCOMMAx(2),RCOMMAx(1),RCOMMAx(0),,,,,,,9,0,WordP,,9,0,WordQ,,9,0,WordR,,9,0,WordS,SERDES Serial STREAM of Data,,,Received First,Received S

32、econd,Received Third,Received Forth,,Received 9 bit Last,Received 0 bit First,,,,,,8,8,,8,18,,8,28,,8,38,K_Ctrl,K_Ctrl,,,,,10,20,30,,Agenda,I/O OverviewSERDES & CDR FundamentalSERDES MeasurementsHow to Evaluate a

33、SERDES Device?High Speed Design Consideration,Eye Diagrams,Eye Diagrams Measure the Quality of a Differential SignalMaximum Eye Height (Vp-p Diff.) and Width Ensures Valid Logic LevelsLong Signal Paths Degrade the Eye

34、 Opening at the Receiver EndTime Base is Unit Interval (UI), which is the Inverse of the Clock FrequencyData falling within the Eye will be Received without Error (BER<1E-12)Data Pattern Eye-Opening provid

35、es a good measure of Signal QualityPre-emphasis typically results in a ‘wider’ eye,200mV / 0.4UI Represents the ORCA FPSC SERDES Minimum Receiver Requirement,Eye Diagrams - Lab Experiment,Experiments were conducted to

36、further characterize the SERDES macro cell in the ORT82G5 device and serve as a basis for future device characterization Test EquipmentORT82G5 evaluation Board.Tyco Electronics XAUI backplane with two port cardsHPE36

37、48A Power suppliesHP8133A Clock sourceTemptronic E3648A Thermal SoakerPicoSecond 5575A Bias-TAgilent 86100A DCA OscilloscopeResults published in Lattice document, TN1027 (available on web),,Eye-Diagram Test Setup,E

38、ye Diagrams - Test Setup Parameters,ConditionsORT82G5 680 PBGAM plastic ball grid array (wire-bond), -3 speed gradePower Supply = 1.5 VAmbient Temperature = 25 degree CData Pattern = PRBS 2^32 - 1 with 8B/10B encodi

39、ngVarying Data Rate and Pre-Emphasis Levels PCB SpecificationThe 2 inch PWB section (port card) is composed of 6 mil wide (1/2 oz. copper thickness) 100 Ohm differential impedance tracesBackplane - 200 mils thick, 14

40、 layers, Nelco 4000-6 FR4All signal layers are 10 mil wide (1/2 oz. copper thickness) traces designed for 100 Ohm differential impedanceAll signal layers buried and surrounded by GND planesPort Card - 93 mils thick, 1

41、4 layers, Nelco 4000-4 FR4Total trace length: 40 inches,Eye Diagrams - ORT82G5 Receiver Eye Patterns,An Illustration of Pre-Emphasis Resulting in Larger Eye Openings,Baseline,Better,Best,Eye Diagrams - Drive Length,3.0

42、GHz [2],40 (FR-4),ORSO82G5,622 MHz,75 ft (coax),ORT8850,3.7 GHz,40 (FR-4) [1],ORT82G5,Speed,Distance (inches),Product,,,,,,,,,,[1]: Not tested to failure [2]: Simulated value,,PLL Jitter - Clock Jitter,Jitter is criti

43、cal to the SONET, GbE, FiberChannel and Infiniband protocols yet the equipment suited for SERDES backplane jitter testing is in it’s infancyJitter is specified by several components:(DJ)- Deterministic Jitter(DCD)-Dut

44、y Cycle Distortion(DDJ)- Data Dependant Jitter(RJ)- Random Jitter(PJ)- Periodic/Sinusoidal Jitter(TJ)- Total JitterSpecs for Fiberchannel, Infiniband, SFI-5, and XAUI are all differentBERT (Bit Error Ratio Tester)

45、One of the key pieces of hardware used for generating errors and quantifying the failures. This hardware is used in the testing of jitter specs.BER (Bit Error Rate)The ratio of the bits received in error to the total n

46、umber of bits received,PLL Jitter - Jitter Table,0.734 UI,>= 0.15 UI,>=0.65UI,0.65UI,0.65UI,0.70UI,RX TJ tolerance,,,>=0.55UI,,,,RX DJ+RJ tolerance,,,>0.10UI(>1.875Mhz),,,0.10UI(>Baud Frequency / 1667

47、),RX PJ tolerance,,,,,,0.22UI,RX RJ tolerance,0.5 UI,,>=0.37UI,TBD,0.41UI,0.38UI,RX DJ tolerance,0.17 UI,0.15 UI,<=0.35UI/0.55UI,0.35UI,0.35UI,0.65UI,TX TJ,,<=0.17UI/0.37UI,0.17UI,0.17UI,0.38UI,TX DJ,2.5 Gbps,ST

48、M-16/STS-48 (2.488 Gbps),2.5 Gbp/s (data only, no OH),2.5 Gbp/s,2.5 Gbp/s,1.0625 Gb/s 2.125 Gbp/s,Data Rate,Lattice part,SONET/SDH,XAUI Near/far-end,SFI-5,Infiniband,Fiber Channel,Spec,,,,,,,,,,,,,,,,,,,PJ mask as a fun

49、ction of frequency for XAUI application,IU = Internal Unit…duration is equal to one clock period,Power - Pre-emphasis & Half Amplitude,Further power savings can be realized by taking the following features into consi

50、deration: Pre-EmphasisThree settings available (0%, 12.5%, 25%) in FPSC SERDESUseful feature that compensates for inherent signal loss that occurs over long trace lengthsMore pre-emphasis means more power dissipati

51、on per SERDES channel Half-Amplitude ModeThis mode is configurable via a register bit Used to reduce power dissipation when transmission medium has minimal attenuation,Power - Pre-emphasis Effects on SERDES Performa

52、nce*,Pre-Emphasis EffectsAssists in compensating for signal attenuation when driving long trace lengthsWhen it comes to pre-emphasis, more isn’t always better !,Power - Pre-emphasis Effects on SERDES Performance*,Altho

53、ugh pre-emphasis is a valuable tool, certain conditions do not require or more importantly, benefit from the use of pre-emphasis The diagrams below illustrate the negative effects it may have on signal integrity when

54、it is not required,Pre-Emphasis: OFF,Pre-Emphasis: ON,,Agenda,I/O OverviewSERDES & CDR FundamentalSERDES MeasurementsHow to Evaluate a SERDES Device?High Speed Design Consideration,Eye Diagrams,This is an Eye Dia

55、gramIt depicts data transitionsIt is a tool to analyze SERDES and backplane performanceIt is analogous to the clock and data scope displays used for Tco and Tsu measurements in parallel systemsThe Display is persiste

56、ntIt holds all data points collectedThe color indicates how often a location is overwrittenThe Height & Width of the Eye translate into the Quality of the signal,,Data Eye,Receiver Eye-Diagram,Unit Interval (UI) i

57、s the Normalized Bit Period, I.e., inverse of Clock Frequency:1 UI for a 1 Gbps Eye Diagram is 1 nS0.4 UI for a 1 Gbps signal is 400 pS (0.4nS)0.4 UI for a 2 Gbps signals is 200 pSData Falling Outside the Eye Will be

58、 Received without Error (BER<1E-12)Data Pattern Eye-Opening (Receiver End) Provides a Good Measure of Signal QualityHighlights the Ability of a Data Link for Error-Free TransferSpecs for an Eye are theEye Width, m

59、easured in UI or pSEye Height, measured in mV,Graphical View of SERDES Receiver Input Requirements,Eye Diagrams,There is Often Confusion Between a Transmitted and Receive Eye Definition and Eye Size…On the transmit siz

60、e, the larger the eye opening transmitted, the betterOn the receive size, the larger eye opening received the better…However…The smaller the requirement for the eye-opening at the receiver, the better,Other Parameters

61、,Bit Rate or Transmit/receive bit clockThe maximum rate at which serial data can be streamedPLL clock or input clockThe Reference clock frequency required to generate a given serial bit ratePath lengthThe maximum le

62、ngth over which data can be transmitted, at a given rate without, or within an acceptable error limitThat is 3.7 Gbps over 34”,Other Parameters,Pre-emphasisA means to enhance the high-frequency context of the transmit

63、ted signal to compensate for limited backplane frequency responseTypically given as: 0%, 12.5%, 25%, etcMore Pre-emphasis Settings is NOT always better,No Pre-EmphasisEye Width:201psEye Height: 152.2mV,12.5% Pre-Emph

64、asisEye Width: 232ps Eye Height: 204.2mV,25% Pre-EmphasisEye Width: 234psEye Height: 268.2mV,Test Equipment,,,,The Bias T Circuit provides the proper 1.5V termination for a CML output buffer. It then removes the DC c

65、omponent for the scope,Cabling,Cable Matching is CriticalAt 3.125 Gbps, the Symbol length is Approximately 300 pSTypically, Signals travel down cables at 170pS per InchThis means that a 1” difference in cable length

66、corresponds to a fully destructive differenceThis translates to reduced eye height and width and…Increased Error rate, reduced drive length and reduced bandwidth,,,Agenda,I/O OverviewSERDES & CDR FundamentalSERDE

67、S MeasurementsHow to Evaluate a SERDES Device?High Speed Design Consideration,High-Speed PCB Design,Microstrip or Stripline RoutingMicrostrip Routing Refers to a Trace Routed on an Outside Layer of the PCB Separated b

68、y a Dielectric From the Reference Plane (GND or VCC). Stripline Routing Refers to a Trace Routed on an Inside Layer With Two Reference Planes,Higher Capacitance,Longer Delay, Better Impedance control, Cleaner signals

69、,Lowest Delays,,Best for SERDES Signals,,PCB Trace Geometry,Differential signal trace-pairs with controlled impedance can be arranged in a number of different configurations:Edge Coupled Microstrip (Top-layer)Edge Coup