[教育]折疊式級聯(lián)運放的仿真_運放基本仿真步驟ppt

1、折疊式級聯(lián)運放的仿真,,The Typical Performance of Op-Amp,Open-Loop Differential Gain (AV)Common-mode Rejection Ratio (CMRR)Power Signal Rejection Ratio (PSRR)Phase Margin (PM)Input Common Mode Range (ICMR)Output Swing Range (O

2、SR)Input/Output Impedance (CIN/ROUT)Slew RateNoise,The Schematic of Folded Cascode Op-Amp,,In order to decease the power Consumption, IBIAS is only 30nA.,Create Schematic and Symbol in Spectre,,,To create a symbol of

3、 a schematic: From Design->Create Cellview->From Cellview,Open-Loop Differential Gain,DC Sweep VP -VN (large signal) AC Sweep VP -VN with fixed frequency (small signal),,Two methods of simulating Open-Loop Diff

4、erential Gainis available in ADE (Analog Design Environment),Test-Bench of Open-Loop Differential Gain (method 1),,DC Sweep VP -VN (large signal),In this method, VP=VCM_IN +x, and VN=VCM_IN-xWhere, VCM_IN is the commo

5、n voltage, x is a design variables.,,,Setup VN,Setup VP,ADE of Open-Loop Differential Gain (method 1),,To add a model for the simulation From ADE->Setup->Model libraries,To create a DC SweepFrom ADE->Analyses

6、->Choose->DC,,,Waveform of Open-Loop Differential Gain (method 1),Where,,Differential Gain is 71.56dB,,To obtain VCOM_OUT From Calculator->Special Functions->Value,VOUT -VCOM_OUT,,To obtain DC gain From

7、Calculator->Special Functions->deriv,Test-Bench of Open-Loop Differential Gain (method 2),,AC Sweep VP -VN with fixed frequency,,,Setup VN,Setup VP,In this method, VP=VCM_IN+ x +VAC, and VN=VCM_INWhere, VCM_IN i

8、s the input common voltage, x is a design variables, VAC is a AC voltage for AC Sweep.,ADE of Open-Loop Differential Gain (method 2),,To add a model for the simulation From ADE->Setup->Model libraries,To create

9、a AC SweepFrom ADE->Analyses->Choose->AC,,,FixedFreq,,Waveform of Open-Loop Differential Gain (method 2),Differential Gain is 65.56dB,The results of the two methods are different, In fact, method 1 is more acc

10、urate for DC gain.,Common-mode Rejection Ratio,,,You can get detail illustration from “CMOS Analog Circuit Design”, Phillip E. Allen, Oxford University Press, Inc.,Test-Bench of CMRR,,,Where,,VCOM_IN is the input common

11、 voltage, VAC is a AC voltage for AC Sweep.,ADE of CMRR,,To add a model for the simulation From ADE->Setup->Model libraries,To create a AC SweepFrom ADE->Analyses->Choose->AC,,,Waveform of CMRR,1/CMRR,C

12、MRR,,To obtain CMRR:From Calculator->1/x,1/CMRR and CMRR plot directly.,Waveform of CMRR,To obtain magnitude Plot of CMRR: From Calculator->dB20,Frequency response of CMRRThe CMRR is 72.14dB at low frequency rang

13、e.,To obtain phase Plot of CMRR: From Calculator->phase,,,Power Signal Rejection Ratio,,,You can get detail illustration from “CMOS Analog Circuit Design”, Phillip E. Allen, Oxford University Press, Inc.,Test-Bench

14、of PSRR,Where,,VAC is a AC voltage for AC Sweep, and VDC is a DC voltage,,ADE of PSRR,,To add a model for the simulation From ADE->Setup->Model libraries,To create a AC SweepFrom ADE->Analyses->Choose->

15、AC,,,Waveform of PSRR,1/PSRR,PSRR,,To obtain CMRR:From Calculator->1/x,1/PSRR and PSRR plot directly.,Waveform of PSRR,To obtain magnitude Plot of PSRR: From Calculator->dB20,Frequency response of PSRRThe CMRR is

16、 79.17dB at low frequency range.,To obtain phase Plot of PSRR: From Calculator->phase,,,Phase Margin of Open-loop frequency Response,,,Where, VCM_IN is the input common voltage, VAC is a AC voltage for AC Sweep,And

17、CL is the loading capacitor.,Test-Bench of PM,,,,VCM_IN,VAC,The dominant pole is controlled by CL in folded Cascode op amp.,ADE of PM,,To add a model for the simulation From ADE->Setup->Model libraries,To create

18、 a AC SweepFrom ADE->Analyses->Choose->AC,,,Waveform of PM,To obtain magnitude Plot of open-loop: From Calculator->dB20,open-loop frequency responseThe PM is 74o when CL is 5pf.,To obtain phase Plot of open

19、-loop: From Calculator->phase,,,There have two poles in open-loop frequencyresponse, one is the dominant pole of output net,and the another is the mirror pole caused by active current mirror.,Input Common-mode Ran

20、ge,,,Where, x is a design variables and CL is the loading capacitor.,Test-Bench of ICMR,,ADE of ICMR,,To add a model for the simulation From ADE->Setup->Model libraries,To create a DC SweepFrom ADE->Analyses-

21、>Choose->DC,,,Waveform of ICMR,,,,,ICMR,The input common-mode range is 0~4.2V,Output Swing Range,,,Where, VCM_IN is the input common voltage, x is a design variables.,To obtain OSR,Test-Bench of OSR,,DC Sweep VP -V

22、N,In this method, VP=VCM_IN +x, and VN=VCM_IN-xWhere, VCM_IN is the common voltage, x is a design variables.,,,Setup VN,Setup VP,ADE of OSR,,To add a model for the simulation From ADE->Setup->Model libraries,To

23、create a DC SweepFrom ADE->Analyses->Choose->DC,,,Waveform of OSR,You can get the left waveform from page 8.,,,,,OSR,The output swing range is from 842.5mV to 4.381V.,PS: OSR is dependence of applications and

24、is not constant.,Input Capacitor,,,Where, VCM_IN is the input common voltage, VAC is AC voltage for AC Sweep.,Test-Bench of CIN,,,,VCM_IN,VAC,ADE of CIN,,To add a model for the simulation From ADE->Setup->Model l

25、ibraries,To create a AC SweepFrom ADE->Analyses->Choose->AC,,,Waveform of CIN,,The input capacitor is approximate of 5pf,Output Resistance,,,,The schematic of obtaining open-loop output resistance RO.,The equi

26、valent model by using Thevenin form On the op amp.,Thus, simulating ROUT and knowing AV allows one to calculate the output resistance RO of the op amp.,,Test-Bench of ROUT,,,IOUT,,VOUT,,,,200R,R=1G,VIN=0V,ADE of ROUT,,T

27、o add a model for the simulation From ADE->Setup->Model libraries,To create a TRAN SweepFrom ADE->Analyses->Choose->TRAN,,,Waveform of ROUT,,,IOUT,,ROUT,,Slew Rate,,The unity-gain configuration places

28、the severest requirements on stabilityand slew rate because its feedback is the largest, resulting in the largest values of loop-gain, and should always be used as a worst-case measurement.,Test-bench of Slew Rate,,T

29、he input step magnitude is 2V.,ADE of SR,,To add a model for the simulation From ADE->Setup->Model libraries,To create a TranFrom ADE->Analyses->Choose->Tran,,,Waveform of SR,,SR=95.1K V/s,Noise,Thermal

30、 Noise (A) channel noise (id) (A) RS noise (rs) (A) RD noise (rd) Flicker Noise (fn),,,Test-Bench of Noise,,,,VCM_IN,VAC,The dominant pole is controlled by CL in folded Cascode op amp.,ADE of Noise,,To add

31、a model for the simulation From ADE->Setup->Model libraries,To create a NoiseFrom ADE->Analyses->Choose->noise,,,Waveform of Noise,,Output noise,Input-referred noise,To obtain output noise and input-ref