fpga vhdl串口

1、時(shí)鐘 時(shí)鐘 4 分頻 分頻，freqd_dff.vhd 文件clk_in：時(shí)鐘輸入clk_out：時(shí)鐘輸出----------------------------------------------------------------------------------------------------------------------library ieee;use ieee.std_logic_1164.all;library

2、altera;use altera.maxplus2.all;entity freqd_dff isgeneric(n: integer :=2);port(clk_in: in std_logic;clk_out: out std_logic);end freqd_dff;architecture freqd_dff_arch of freqd_dff issignal q: std_logic_vector(0 to n);begi

3、nq(0) <= clk_in;G1: for i in 0 to (n-1) generateUx: dff port map(not q(i+1), q(i), '1', '1', q(i+1));end generate;clk_out <= q(n);end freqd_dff_arch;-------------------------------------------------

4、---------------------------------------------------------------------波特率產(chǎn)生 波特率產(chǎn)生，clock.vhd 文件clk:50m 時(shí)鐘clk_out:4 倍的波特率時(shí)鐘end process;clk_out <= count(31);end clock_arch;串口接收， 串口接收，recvive.vhd 文件clk:4 倍的波特率時(shí)鐘reset:復(fù)位端，低

5、電平’0’復(fù)位rx:串口 rxrx_done:接收完成，1 時(shí)完成接收rx_buf:接收的數(shù)據(jù)---------------------------------------------------------------------------------------------------------------------library ieee;use ieee.std_logic_1164.all;use ieee.std_lo

6、gic_unsigned.all;use ieee.std_logic_arith.all;entity recvive isgeneric(framlent:integer:=8);Port(clk, reset: std_logic;rxbuf: out std_logic_vector(7 downto 0);rx: in std_logic;rx_done: out std_logic);end recvive;archite