體系結(jié)構(gòu)級(jí)圖形圖像加速方法與實(shí)現(xiàn)研究.pdf

1、湖南大學(xué)碩士學(xué)位論文體系結(jié)構(gòu)級(jí)圖形圖像加速方法與實(shí)現(xiàn)研究姓名：趙俊申請(qǐng)學(xué)位級(jí)別：碩士專業(yè)：計(jì)算機(jī)應(yīng)用技術(shù)指導(dǎo)教師：李小堅(jiān)李仁發(fā)20080414體系結(jié)構(gòu)級(jí)圖形圖像加速方法與實(shí)現(xiàn)研究AbstractImageenhancementtechnologyiswidelyusedinindustrynationaldefensetechnologypeople’sdailylives.Howevertheembeddedimageenhancem

2、entsystem’sdeficienciesthattheheavyburdenofMCUweaktransplantationthelimitationofdisplayingfunctionleadtodifficultyinprocessingconsecutivehighqualityimage.UsingimageenhancementchiptohelpMCUaccomplishingthetaskofimageenhan

3、cementcanaccelerateimageprocessingsaveembeddedsystem’sresource.Soitisimptanttomakeresearchonthearchitectureofembeddedimageenhancementchip.Thisthesisintroducesanewarchitectureofembeddedimageenhancementchiptoresolvetheprob

4、lemsoflowspeedofprocessingresourcelimitationweaktransplantation.Inthisarchitecturethefunctionisdividedintoseveralindependentmoduleswhosefunctionisimplementedbylogiccircuit.ThechipcouldhelpMCUtofinishdisplayingtasklighten

5、theburdenofmicroprocess.ItnotonlyacceleratesimageprocessingbutalsosavestheresourceofMCU.Inadditionhavinggeneralcontrolbusdatabusaddressbusintegratedcommthisimageenhancementchipcouldcommunicatewithdifferentembeddedmicropr

6、ocesscouldbeaccesseddirectlybythemicroprocessasapartofmicroprocessaddressingspace.Indertoprovethefeasibilityofproposedarchitectureaprototypeisbuiltoncustomizationboardusingsystemonchiptechnology.Theceofboardiscomposedofa

7、FPGAchipaSDRAMaFLASH.FPGAwkflowisusedtodesignthechipatthesametimeVerilogHardwareDeionLanguageisusedtoconstructanIPceofthegeneralembeddedenhancementchip.Finallyatestplatfmisbuilttotestthechipwhichalsoincludesacommsendings

8、oftwaredevelopedbyTCLlanguage.Thissoftwareisusedtoproducedisplayingcommsendsthecommtogeneralembeddedenhancementchip.Inthetestthefunctionsofimagedisplayingdownloadingtheoperationofthescreencanbeimplementedfastaccdingcomms