外文翻譯--高速數(shù)據(jù)采集系統(tǒng)的設(shè)計(jì)

1、<p>　　中文4300字，2730單詞</p><p>　　畢業(yè)設(shè)計(jì)(論文)外文資料翻譯</p><p>　　附件：1.外文資料翻譯譯文；2.外文原文</p><p>　　高速數(shù)據(jù)采集系統(tǒng)的設(shè)計(jì)</p><p>　　張俊杰，章鳳一，葉家駿</p><p>　?。ㄉ虾４髮W(xué)特種光纖和光纖接入教育部重點(diǎn)實(shí)驗(yàn)室部，

2、上海200072）</p><p>　　摘要：為滿足雷達(dá)信號(hào)采集的要求，設(shè)計(jì)了一種基于PCI總線的12 bit100 MS / s的數(shù)據(jù)采集系統(tǒng)。該系統(tǒng)可實(shí)現(xiàn)6 GB數(shù)據(jù)的實(shí)時(shí)采集和存儲(chǔ)?？删幊踢壿嬈骷刂茢?shù)據(jù)收集，存儲(chǔ)和傳輸。使用PCI主模式的PCI數(shù)據(jù)傳輸，傳輸速率達(dá)到60M字節(jié)/秒，（30兆赫的模擬信號(hào)）收集到的信號(hào)的信噪比可以達(dá)到55 dB。</p><p>　　關(guān)鍵詞：PCI控制

3、器;可編程器件;抖動(dòng)。</p><p><b>　　1.總述</b></p><p>　　隨著通信，雷達(dá)等領(lǐng)域的快速發(fā)展，所需處理模擬信號(hào)的帶寬和動(dòng)態(tài)范圍也越來(lái)越大，DAC采樣速度和精度要求越來(lái)越高。高速度和高精度的數(shù)據(jù)收集所需的存儲(chǔ)器帶寬變得越來(lái)越大，因此，如何提高數(shù)據(jù)存儲(chǔ)器帶寬已經(jīng)成為高速數(shù)據(jù)采集系統(tǒng)設(shè)計(jì)的瓶頸之一。</p><p>　　雷

4、達(dá)系統(tǒng)的數(shù)據(jù)采集系統(tǒng)時(shí)鐘采樣頻率要求是至少100兆赫，對(duì)至少10位DAC分頻。而現(xiàn)有的計(jì)算機(jī)系統(tǒng)滿足不了雷達(dá)系統(tǒng)的實(shí)時(shí)傳輸?shù)囊?。但雷達(dá)信號(hào)的有用信息只占其中一小部分。如圖1，因此，只要將有用信息采集和儲(chǔ)存，則可實(shí)現(xiàn)雷達(dá)信號(hào)樣本實(shí)時(shí)存儲(chǔ)。</p><p><b>　　圖1</b></p><p>　　根據(jù)雷達(dá)信號(hào)采集和存儲(chǔ)的特性，本文設(shè)計(jì)一個(gè)12 bit100 MS

5、/ s的數(shù)據(jù)采集系統(tǒng)。該系統(tǒng)采用了PCI總線連接到計(jì)算機(jī)，數(shù)據(jù)采集系統(tǒng)利用板卡大容量信息對(duì)有用信息進(jìn)行實(shí)時(shí)處理，數(shù)據(jù)采集由系統(tǒng)外部出發(fā)信號(hào)控制。</p><p><b>　　2.數(shù)據(jù)采集卡框架</b></p><p>　　整個(gè)采集系統(tǒng)分為以下四個(gè)部分：模擬信號(hào)調(diào)制部分，時(shí)鐘脈沖處理模塊，數(shù)據(jù)緩存模塊，數(shù)據(jù)傳輸和觸發(fā)模塊。如圖2所示。</p><p&

6、gt;<b>　　圖2</b></p><p><b>　　2.1模擬信號(hào)調(diào)制</b></p><p>　　模擬信號(hào)的調(diào)制包括：模擬信號(hào)前放，信號(hào)數(shù)控增益，單端轉(zhuǎn)差分布。模模擬信號(hào)前置運(yùn)放采用AD9631實(shí)現(xiàn)輸入信號(hào)的阻抗匹配及信號(hào)的低通濾波。在一個(gè)雷達(dá)系統(tǒng)中，從不同的雷達(dá)站收集掃描目標(biāo)的雷達(dá)信號(hào)振幅是不同的，并且為了提高采集系統(tǒng)的信噪比，應(yīng)使A

7、DC的模擬輸入信號(hào)的幅度接近滿幅。所以將一個(gè)壓控增益運(yùn)算放大器AD603芯片加到前置運(yùn)算放大器之后，以調(diào)節(jié)ADC輸入信號(hào)的范圍。電壓控制AD603的增益芯片的模擬帶寬在90 MHz時(shí)， 增益范圍-11 dB一30 dB。由一片8位DAC芯片產(chǎn)生壓控芯片的的增益電壓，DAC的芯片選擇MAX503 MAXIM公司出品，芯片數(shù)字輸入由FPGA控制和產(chǎn)生。數(shù)據(jù)采集系統(tǒng)的ADC 是由AD公司12位100兆赫AD9432 的芯片，該模擬信號(hào)為45M

8、Hz仍然具有65 dB的信噪比。由于該ADC模擬信號(hào)為差分輸入差，因此,從壓控增益芯片AD603輸出的模擬信號(hào)經(jīng)過(guò)單端轉(zhuǎn)差分芯片AD8138連接到ADC芯片上，從ADC輸出的12 bit數(shù)字信號(hào)直接連接到FPGA芯片上。</p><p><b>　　2.2 時(shí)鐘模塊</b></p><p>　　為了增加所述采集系統(tǒng)的靈活性和通用性，該ADC采樣時(shí)鐘芯片可以是從外部時(shí)鐘

9、，也可以從內(nèi)部時(shí)鐘。采樣時(shí)鐘的選擇由板卡跳線器決定。外部時(shí)鐘通過(guò)SMA連接器連接到電路板上，外部時(shí)鐘信號(hào)為TTL電平，由于ADC的采樣時(shí)鐘需要PECL電平，因此，外部時(shí)鐘時(shí)鐘由PECL電平轉(zhuǎn)換芯片MClOELl6連接到時(shí)鐘選擇模塊。 ADC的內(nèi)部時(shí)鐘是由該系統(tǒng)的數(shù)控時(shí)鐘模塊生產(chǎn)。 時(shí)鐘模塊選擇頻率合成器是NC SY89429。時(shí)鐘輸出的范圍在25兆赫至400兆赫之間，用于PECL輸出信號(hào)，可直接連接到ADC的采樣時(shí)鐘。該頻率合成器的時(shí)鐘

10、輸出可被芯片的11位數(shù)字信號(hào)控制，可以精確調(diào)節(jié)輸出時(shí)鐘精度至1兆赫茲。 11數(shù)字信號(hào)由FPGA控制。在數(shù)據(jù)采集系統(tǒng)中，特別是在高速數(shù)據(jù)采集系統(tǒng)，該時(shí)鐘是一個(gè)非常重要的信號(hào)，不同時(shí)鐘抖動(dòng)相差較大。當(dāng)采集系統(tǒng)的輸入模擬信號(hào)帶寬較大時(shí)，在計(jì)算采集系統(tǒng)的信噪比時(shí)鐘抖動(dòng)不能被忽略。量化噪聲的因素也需要考慮“1，12位的ADC，當(dāng)輸入信號(hào)的頻率為40 MHz時(shí)，信噪比和采樣時(shí)鐘抖動(dòng)曲線如圖3所示，橫坐標(biāo)為對(duì)采樣時(shí)鐘抖動(dòng)，y坐標(biāo)為采集系統(tǒng)的信噪比。從

11、圖3中可以看出，為使ADC的采集系統(tǒng)的信噪比大</p><p><b>　　圖3</b></p><p>　　2.3高速數(shù)據(jù)緩存模塊</p><p>　　高速ADC數(shù)據(jù)存儲(chǔ)由A1tera公司生產(chǎn)的Cyclone FPGA芯片控制。如圖4的邏輯結(jié)構(gòu)</p><p>　　數(shù)據(jù)采集系統(tǒng)使用MICRON公司的2片MT48LC4M

12、16A2SDRAM并聯(lián)作為系統(tǒng)的片上存儲(chǔ)器。并聯(lián)SDRAM內(nèi)存位寬為32位，16 MB的容量，100 MHz的時(shí)鐘頻率。比的SRAM芯片的SDRAM的芯片具有更高的工作速度，容量更大，為系統(tǒng)提供了設(shè)計(jì)的靈活性。為了改善的SDRAM的傳輸帶寬，SDRAM控制器突發(fā)長(zhǎng)度（burst length)設(shè)為8，這個(gè)突發(fā)長(zhǎng)度是除整頁(yè)的讀/寫的最大突發(fā)長(zhǎng)度。從高速12位ADC過(guò)來(lái)100MHz的信號(hào)在觸發(fā)使能信號(hào)有效時(shí)，由存寫控制模塊把ADC數(shù)據(jù)流的位

13、寬擴(kuò)展l倍，擴(kuò)展后的24比特采樣數(shù)據(jù)寫入FIF0中。當(dāng)存儲(chǔ)器讀控模塊檢測(cè)到在FIF0存儲(chǔ)數(shù)據(jù)深度得到大于8時(shí)，從剩余的FIFO 8個(gè)24bit位的數(shù)據(jù)讀出，并使用wishbone（WB）14總線將數(shù)據(jù)傳送到SDRAM控制器，由SDRAM控制器把該數(shù)據(jù)寫入到外部的SDRAM芯片。雖然外部SDRAM芯片的數(shù)據(jù)總線寬度為32位，但實(shí)際使用只有24位，也就是理論上的SDRAM總線傳輸帶寬為300 MB /秒?？紤]到SDRAM的刷新和突發(fā)傳輸開銷

14、，實(shí)際上可以實(shí)現(xiàn)200MB / s，而ADC的采樣數(shù)據(jù)傳輸帶寬為1</p><p>　　2.4數(shù)據(jù)傳輸和觸發(fā)模塊</p><p>　　使用AMCC公司的PCI主控器件s5933傳輸采樣數(shù)據(jù)到計(jì)算機(jī)的內(nèi)存中。 S5933是一種特殊的功能非常強(qiáng)大的，靈活運(yùn)用PCI總線的控制器芯片。它完全符合PCI局部總線規(guī)范2.1l，不僅可以做PCI總線從設(shè)備，并且可以做PCI總線主設(shè)備進(jìn)行數(shù)據(jù)傳輸。 S59

15、33擁有三個(gè)接口：PCI總線接口，ADDON總線接口和外部NVRAM參數(shù)配置界面。 PCI總線接口和連接到該P(yáng)CI總線的計(jì)算機(jī)的插槽相連。計(jì)算機(jī)與用戶端可以通過(guò)ADDON總線接口的FIF0通道、PATH—THRU通道進(jìn)行相互通信。PCI總線通過(guò)使用PATH . THRU渠道實(shí)現(xiàn)和客戶信息的交互?？蛻舳死肍IFO通道把本地存儲(chǔ)數(shù)據(jù)通過(guò)計(jì)算機(jī)的PCI總線傳遞到計(jì)算機(jī)內(nèi)存中。計(jì)算機(jī)使用S5933的PASS。TRU操作控制FPGA的內(nèi)部寄存器

16、。當(dāng)計(jì)算機(jī)發(fā)出的PCI地址落在PASS—THRU定義的某個(gè)區(qū)中時(shí)，s5933通過(guò)PTATN向FPGA的PATH—TRU控制及譯碼邏輯發(fā)出請(qǐng)求。PATH—TRU控制與譯碼邏輯根據(jù) PTADR信號(hào)判斷本次操作是PATH-TRU讀操作還是寫操作，利用PTADR信號(hào)獲取本次PATH—THRU操作的地址信息(該</p><p>　?。?）根據(jù)計(jì)算機(jī)收集到的模擬信號(hào)最大數(shù)值，通過(guò)數(shù)控增益DAC寄存器使ADC的模擬信號(hào)輸入是接

17、近全振幅。</p><p>　?。?）通過(guò)ADC采樣時(shí)鐘寄存器設(shè)定ADC采樣時(shí)鐘工作（如果使用內(nèi)部時(shí)鐘頻率）。</p><p>　?。?）設(shè)置ADC需要收集數(shù)據(jù)的總量：數(shù)據(jù)總量為32位的寄存器，足以滿足現(xiàn)有的雷達(dá)系統(tǒng)的需要，總數(shù)據(jù)寄存器必須是16的倍數(shù)。</p><p>　?。?）通過(guò)模式配置寄存器設(shè)置ADC高速數(shù)據(jù)采集系統(tǒng)的操作模式：設(shè)置ADC的外部觸發(fā)信號(hào)觸發(fā)模

18、式（電平觸發(fā)或邊沿觸發(fā)），設(shè)置ADC采樣信號(hào)的軟件觸發(fā)或硬件觸發(fā)（即外部觸發(fā)），可以控制ADC采樣。</p><p>　?。?）設(shè)置觸發(fā)延遲時(shí)間：雷達(dá)系統(tǒng)的采樣時(shí)間觸發(fā)延時(shí)可以通過(guò)寄存器進(jìn)行設(shè)置</p><p>　　根據(jù)觸發(fā)模塊觸發(fā)條件，采樣的數(shù)據(jù)量和單次觸發(fā)采樣數(shù)量產(chǎn)生觸發(fā)使能信號(hào)，該信號(hào)相當(dāng)于存FIF0寫使能信號(hào)。</p><p>　　計(jì)算機(jī)使用S5933的 P

19、CI主模塊FIF0通道實(shí)現(xiàn)采樣數(shù)據(jù)到計(jì)算機(jī)內(nèi)存的自動(dòng)傳輸。s5933內(nèi)部的FIF0通道寫操作由FPGA完成，讀操作由s5933內(nèi)部控制器完成。一旦檢測(cè)到S5933 WRFULL信號(hào)（F1F0信道滿信號(hào)）是無(wú)效的，或PCI主模塊寫FIF0通道不滿時(shí)，則從非空傳雙時(shí)鐘FIFO讀取數(shù)據(jù)，并寫入到S5933的PI主模塊的寫FIFO的數(shù)據(jù)通道。</p><p>　　高速緩存塊數(shù)記錄SDRAM控制器里面有多少數(shù)據(jù)塊要發(fā)送，在

20、寫入數(shù)據(jù)的一個(gè)塊中，SDRAM的高速緩存塊數(shù)上升1，當(dāng)讀取從SDRAM數(shù)據(jù)的一個(gè)塊，高速緩存塊是減去1。 傳雙時(shí)鐘FIFO的寫控制由傳讀控制邏輯完成。傳讀控制邏輯，傳雙時(shí)鐘FIFO的寫控制由傳讀控制邏輯完成。傳讀控制邏輯只有在采集數(shù)據(jù)沒(méi)有傳輸完畢且傳雙時(shí)鐘FIF0非滿時(shí)，才啟動(dòng)wb讀總線操作，從SDRAM緩沖區(qū)讀取一個(gè)數(shù)據(jù)塊并把該數(shù)據(jù)塊寫入傳雙時(shí)鐘FlF0中。</p><p>　　wishbone總線仲裁模塊實(shí)現(xiàn)

21、wb寫總線與wb讀總線的仲裁，其采用固定優(yōu)先級(jí)的方式，wb寫總線的優(yōu)先級(jí)比wb讀總線的優(yōu)先級(jí)高，保證了采樣數(shù)據(jù)的實(shí)時(shí)本地存儲(chǔ)。</p><p><b>　　3.軟件設(shè)計(jì)</b></p><p>　　為了提高數(shù)據(jù)傳輸速率，并降低了CPU資源占用，數(shù)據(jù)采集是通過(guò)使用PCI主動(dòng)控制方式來(lái)實(shí)現(xiàn)數(shù)據(jù)到計(jì)算機(jī)內(nèi)存的傳輸。然而由于S5933芯片單次傳輸數(shù)據(jù)的最大數(shù)量64 MB，，所

22、以如果你想連續(xù)發(fā)送大于64 MB的數(shù)據(jù)，則需要多次啟動(dòng)主模式數(shù)據(jù)傳輸。在數(shù)據(jù)傳輸?shù)倪^(guò)程中，CPU不進(jìn)行過(guò)程控制。軟件首先執(zhí)行PCI總線掃描，獲得S5933芯片占用 PCI配置的空間地址，然后向操作系統(tǒng)申請(qǐng)用于收集數(shù)據(jù)被傳遞到計(jì)算機(jī)的存儲(chǔ)器的物理空間，并且將該地址映射到s5933PCI主設(shè)備的物理空間。然后軟件配置S5933芯片內(nèi)部寄存器，包括DMA傳輸數(shù)據(jù)量和PCI總線傳輸特性等寄存器，并且可以使s5933PCI主控操作。 S5933等

23、待FPGA發(fā)送采集數(shù)據(jù)，如果S5933內(nèi)置寫FIFO芯片的通道不為空，則發(fā)起PCI總線操作把數(shù)據(jù)傳遞到計(jì)算機(jī)內(nèi)存中。軟件根據(jù)實(shí)際雷達(dá)需求通過(guò)s5933的PASS-TRU操作對(duì)FPGA內(nèi)部相關(guān)寄存器進(jìn)行配置，設(shè)置數(shù)據(jù)采集系統(tǒng)相關(guān)參數(shù)，并觸發(fā)使能FPGA數(shù)據(jù)。雷達(dá)信號(hào)的數(shù)據(jù)采集和存儲(chǔ)由硬件自動(dòng)完成，當(dāng)采樣數(shù)據(jù)到達(dá)S5933單次數(shù)據(jù)傳輸量時(shí)，S5933向計(jì)算機(jī)申請(qǐng)一個(gè)中斷。軟件在中斷處理程序</p><p><b

24、>　　4性能分析與測(cè)試</b></p><p>　　在本文中，數(shù)據(jù)采集系統(tǒng)的采樣頻率為25兆赫到100兆赫，可以動(dòng)態(tài)地按1兆Hz步長(zhǎng)進(jìn)行調(diào)整。采集系統(tǒng)來(lái)支持多個(gè)外部觸發(fā)模式，外部觸發(fā)方式由可編程邏輯器件動(dòng)態(tài)設(shè)計(jì)。板卡內(nèi)置的32 MB內(nèi)存儲(chǔ)器決定了有用信息的采集時(shí)間，在采樣頻率100兆赫時(shí)，有用信息獲取時(shí)間可以達(dá)到160 ms.</p><p>　　該采集系統(tǒng)可實(shí)時(shí)傳輸?shù)臄?shù)

25、據(jù)量受可編程邏輯器件寄存器的大小的和計(jì)算機(jī)內(nèi)存的大小限制，該系統(tǒng)采用了32位寄存器，能夠傳輸?shù)臄?shù)據(jù)理論總量為個(gè)采樣點(diǎn)，即6 GB。。</p><p>　　設(shè)計(jì)的數(shù)據(jù)采集系統(tǒng)經(jīng)過(guò)測(cè)試，PCI傳輸速度是60 MB / s的（多次DMA數(shù)據(jù)傳輸），在100兆赫的工作頻率下為了實(shí)現(xiàn)雷達(dá)信息的實(shí)時(shí)采集，雷達(dá)系統(tǒng)的掃描周期與有用信息采集時(shí)間之比應(yīng)該大于2.5。本系統(tǒng)涉及的雷達(dá)有用信息采樣時(shí)間為72μs，雷達(dá)掃描周期為360

26、us，因此，在本文中，高速數(shù)據(jù)采集系統(tǒng)能夠滿足雷達(dá)系統(tǒng)的實(shí)時(shí)存儲(chǔ)和傳輸?shù)男枨蟆y(cè)試表明，該系統(tǒng)信噪比超過(guò)55分貝（30兆赫的模擬信號(hào)），該雷達(dá)系統(tǒng)能夠滿足需求的性能。</p><p><b>　　5 .結(jié)束語(yǔ)</b></p><p>　　在本文中，根據(jù)雷達(dá)信號(hào)的特性來(lái)完成高速數(shù)據(jù)采集系統(tǒng)的設(shè)計(jì)。該系統(tǒng)可以完成實(shí)時(shí)雷達(dá)信號(hào)的采集和存儲(chǔ)，該系統(tǒng)的SNR性能達(dá)到了雷達(dá)的需求

27、。由于采用可編程邏輯器件，所以該系統(tǒng)能夠滿足其他場(chǎng)合的需要。</p><p><b>　　參考文獻(xiàn)</b></p><p>　　[1] 張?zhí)N玉、王元祥、胡修林．高速數(shù)據(jù)采集系統(tǒng)中的存儲(chǔ)瓶頸問(wèn)題及其解決[J]．微計(jì)算機(jī)應(yīng)用，2007，28(6)：610—613．</p><p>　　[2]張俊杰，喬 崇，劉尉悅，等．高速數(shù)據(jù)采集系統(tǒng)時(shí)鐘抖動(dòng)研究[

28、J]．中國(guó)科學(xué)技術(shù)大學(xué)學(xué)報(bào)，2005，35(2)：227—231．</p><p>　　[3]Dalt N D．on the Jitter Requirements of the Sampling Clock for Analog-t0-Digital Conveners[J]．IEEE Transactions on circuits and systems，2002，49(9)：1354-1360．<

29、;/p><p>　　[4]陳雙燕，王東輝·張鐵軍，等．基于WISHBONE的可兼容存儲(chǔ)器控制器設(shè)計(jì)[J]·計(jì)算機(jī)工程，2006，32(18)：240-242．</p><p>　　[5]張平，劉寄，伍衛(wèi)華·基于s5933的高速數(shù)據(jù)采集卡控制設(shè)計(jì)[J]．重慶大學(xué)學(xué)報(bào)，2006，29(10)：69—73．</p><p>　　High spee

30、d data acquisition system design</p><p>　　Zhang Jun Jie .Zhang Yi Feng. Ye Jia Jun</p><p>　　(Special optical fiber and optical access to the ministry of education key laboratory of Shanghai univ

31、ersity,Shanghai 200072)</p><p>　　Abstract: to meet the requirements of radar signal acquisition, design a 12 bit100 Ms/s data collection system based on PCI bus. The system can realize 6 GB of data real-time

32、 collection and storage. Programmable logic devices to control data collection, storage and transmission. PCI data transmission using PCI main mode, transmission rate reached 60 MB/s, the signal-to-noise ratio of the sig

33、nal collected at 55 dB (30 MHz analog signals).</p><p>　　Key words: the PCI controller; Programmable device; jitter.</p><p><b>　　Summarize</b></p><p>　　With the rapid de

34、velopment of communication, radar, and other fields, to deal with analog signal bandwidth and dynamic range is more and more big, the DAC sampling speed and precision demand is higher and higher. High speed and high prec

35、ision data gathering the required memory bandwidth is becoming more and more big, therefore, how to improve the data memory bandwidth has become one of the bottleneck of high-speed data acquisition system design. </p&

36、gt;<p>　　Radar system requirements of data acquisition system clock sampling frequency is 100 MHZ, at least for at least 10 bit DAC points frequency. While the existing computer system satisfies the requirement of

37、 the real-time transmission of radar system. But radar signal useful information make up only a small part of them. As shown in figure 1, therefore, as long as the collection and storage of useful information can realize

38、 the real-time radar signal samples storage.</p><p><b>　　figure 1</b></p><p>　　According to the characteristics of radar signal collection and storage, this paper designed a 12 bit10

39、0 Ms/s of the data acquisition system. The system USES the PCI bus are connected to the computer, the large capacity data acquisition system by using the interface card information useful for real-time information proces

40、sing, data acquisition system external signal control.</p><p>　　2. Framework, Data acquisition card</p><p>　　The whole collection system is divided into the following four parts: Part analog sig

41、nal modulation, The clock processing module, Data caching module, Data transmission and trigger module. As shown in figure 2.</p><p><b>　　figure 2</b></p><p>　　2.1 Analog signal mod

42、ulation</p><p>　　Analog signal modulation, including: before the analog signals and signal numerical control gain, and single side slip distribution. Analog signal pre op-amp input signal of the impedance ma

43、tching is realized by using AD9631 low-pass filtering and signal. In a radar system, scanning the target and radar stations from different collected radar signal amplitude is different, and in order to improve the signal

44、-to-noise ratio of the acquisition system, should make the simulation of the ADC input sig</p><p><b>　　2.2 RTC</b></p><p>　　In order to increase the acquisition system's flexibi

45、lity and universality, the ADC sampling clock chip can be from an external clock, also can from the internal clock. The choice of the sampling clock is decided by the board jumper wire device. Through a SMA connector is

46、connected to the external clock collection on the board, the external clock signal into TTL level, due to the ADC sampling clock need to PECL level, therefore the external clock by TTL to PECL level conversion chip MClOE

47、Ll6 sel</p><p><b>　　figure 3</b></p><p>　　2.3 High speed data cache module</p><p>　　High-speed ADC data storage is a Cyclone FPGA chip by A1tera company control. Logica

48、l structure as shown in figure 4</p><p><b>　　figure 4</b></p><p>　　Data acquisition system using MT48LC4M16A2SDRAM parallel 2 tablets up to MICRON company as a system of on-chip memo

49、ry. Parallel SDRAM memory bits wide is 32 bit, the capacity of 16 MB, the clock frequency of 100 MHz. Than SRAM chip SDRAM chips have higher working speed, larger capacity, provides more flexibility for system design. In

50、 order to improve the transmission bandwidth of SDRAM, the breaking length of SDRAM controller (burst length) at eight The burst length is in addition to the full pa</p><p>　　2.4 Data transmission and trigg

51、er module</p><p>　　Using AMCC company s5933 PCI master devices transmit the sampled data to a computer's memory. S5933 is a kind of special function is very strong, flexible use of PCI bus controller chi

52、p. It completely conforms to the PCI local bus specification 2.1 l, from already can do PCI bus device, and can do PCI bus master device for data transmission. S5933 have three interfaces: PCI bus interface, ADDON bus in

53、terface and external NVRAM parameters configuration interface. The PCI bus interface and the com</p><p>　　Computer using s5933 PASS. TRU operation control of the FPGA internal registers. When computer PCI ad

54、dress on PASS - THRU define a zone, s5933 to the PATH of the FPGA - through PTATN TRU and decoding logic control request. PATH - TRU and decoding logic control according to determine the operating PATH - PTADR signals TR

55、U to read or write operation, using PTADR signal to obtain the PATH - THRU operating address information (the address stored in s5933 PATH - TRU internal registers). The FPGA usin</p><p>　　Computer using s59

56、33 PASS. TRU operation control of the FPGA internal registers. When computer PCI address on PASS - THRU define a zone, s5933 to the PATH of the FPGA - through PTATN TRU and decoding logic control request. PATH - TRU and

57、decoding logic control according to determine the operating PATH - PTADR signals TRU to read or write operation, using PTADR signal to obtain the PATH - THRU operating address information (the address stored in s5933 PAT

58、H - TRU internal registers). The FPGA usin</p><p>　　(1) according to the biggest computer to analog signals collected, through nc gain DAC register ADC input analog signal input is close to full amplitude.&l

59、t;/p><p>　　(2) through the ADC sampling clock registers set ADC sampling clock working (if using the internal clock frequency.</p><p>　　(3) set the ADC to gather the amount of data: data volume for

60、 32-bit registers, enough to meet the needs of the existing radar system, the total data registers must be a multiple of 16.</p><p>　　(4) through the pattern configuration register setting the operation mode

61、 of the ADC high-speed data acquisition system: set up the ADC external trigger signal trigger mode (level trigger or edge-triggered), set up the ADC sampling signals to trigger software or hardware trigger (that is, the

62、 external trigger), can control the ADC sampling.</p><p>　　(5) sets the trigger delay period: radar system the trigger delay time of sampling time can be set through the register </p><p>　　Trigg

63、er module according to the trigger condition, the number of sampling data amount and single trigger sampling trigger enabling signal, the signal is equivalent to save FIF0 write enable signal.</p><p>　　Compu

64、ter using s5933 PCI main module FIF0 channel automatic transmission to realize sampling data to the computer's memory. S5933 FIF0 channel within the write operations performed by FPGA, the read operation performed by

65、 internal controller s5933. Once detected s5933 WRFULL transcription control module (F1F0 channel full signals) is invalid, or PCI main module to write FIF0 channels is not full, the double clock FIFO reads data from the

66、 airborne, and the data written to the s5933 PI main module</p><p>　　Cache block number record SDRAM controller inside how much a data block to be transmitted, in to write a block of data, the SDRAM cache bl

67、ock number l, when read a block of data from SDRAM, cache blocks is minus l. Double clock FIFO capacity of 2 KB, rate matching and data buffer implementation, speaking, reading and writing. Preach dual clock FIFO write c

68、ontrol by read complete control logic. The read only in data transmission to complete control logic and the double clock FIF0 is not full to l</p><p>　　Wishbone bus arbitration module realizes the wb write b

69、us and wb bus arbitration, and read it with the method of fixed priority, wb write bus priority than wb read bus priority, guarantee the real-time sampling data stored locally.</p><p>　　Software design</p

70、><p>　　In order to improve data transmission rate and reducing the number of CPU resources, data acquisition is realized by using PCI master way of data to the computer's memory. However because of s5933 si

71、ngle chip 64 MB, the maximum amount of data transferred so if you want to Continuous transmission is larger than 64 MB of data, then need to start the main mode data transmission for many times. In the process of data tr

72、ansmission, the CPU does not carry on the process control. Software to perform PC</p><p>　　4 Performance analysis and testing</p><p>　　In this paper, the data acquisition system sampling freque

73、ncy for 25 MHz to 100 MHz, can be dynamically adjusted by l MHz step length. Acquisition system to support multiple external trigger mode, the external trigger mode by the dynamic design of programmable logic device. Boa

74、rd built-in 32 MB on chip memory determines the useful information collection time, under the sampling frequency 100 MHZ, useful information acquisition duration can achieve 160 ms.The acquisition system can real-time tr

75、an</p><p>　　Design of data acquisition system is tested, the transmission speed PCI is 60 MB/s (multiple DMA data transmission), under the l00 MHz operating frequency, in order to achieve real-time data acqu

76、isition of radar information radar system scan cycles and the ratio of the useful information collection time should be greater than 2.5. This system involves the sampling time is 72 mu s useful information radar, radar

77、scanning cycle is 360 us, therefore, in this paper, the high-speed data acquisition s</p><p><b>　　5 TAG</b></p><p>　　In this paper, according to the characteristics of the radar sig

78、nal to complete the design of high-speed data acquisition system. This system can accomplish real-time radar signal acquisition and storage, the system SNR performance achieve the demand of the radar. Due to using progra

79、mmable logic devices, so the system can meet the needs of other occasions. </p><p>　　References </p><p>　　[1] Zhang Yunyu, Wang Yuanxiang, Hu Xiulin. High-speed data acquisition syst

80、em of storage bottleneck problem and its solution[J]．Microcomputer Applications，2007，28(6)：610—613．</p><p>　　[2]Zhang Junjie, Joe chung, LiuWei yue, etc. High speed data acquisition system clock jitter[J]．Jo

81、urnal of university of science and technology of China，2005，35(2)：227—231．</p><p>　　[3]Dalt N D．on the Jitter Requirements of the Sampling Clock for Analog-t0-Digital Conveners[J]．IEEE Transactions on circ

82、uits and systems，2002，49(9)：1354-1360．</p><p>　　[4]Chen Shuangyan, wang donghui Zhang Tiejun, etc. Based on the WISHBONE compatible memory controller design[J]·computer engineering，2006，32(18)：240-242．&