電氣專(zhuān)業(yè)畢業(yè)設(shè)計(jì)外文翻譯9

1、<p><b>　　附錄3 英文資料</b></p><p>　　Power Management Techniques and Calculation</p><p>　　Relevant Devices</p><p>　　This application note applies to the following device

2、s: C8051F000, C8051F001, C8051F002, C8051F005, C8051F006, C8051F010, C8051F011, C8051F012, C8051F012, C8051F015, C8051F016, and C8051F017.</p><p>　　Introduction</p><p>　　This application note di

3、scusses power management techniques and methods of calculating power in a Cygnet C8051F00x and C8051F01x Sock. Many applications will have strict power requirements, and there are several methods of lowering the rate of

4、power consumption without sacrificing performance. Calculating the predicted power use is important to characterize the system’s power supply requirements.</p><p>　　Key Points</p><p>　　? Supply

5、voltage and system clock frequency strongly affect power consumption.</p><p>　　? Cygnet’s Sock’s feature power management modes: IDLE and STOP.</p><p>　　? Power use can be calculated as a functi

6、on of system clock frequency, supply voltage, and enabled peripherals.</p><p>　　Power Saving Methods</p><p>　　CMOS digital logic device power consumption is affected by supply voltage and system

7、 clock (SYSCLK) frequency. These parameters can be adjusted to realize power savings, and are readily controlled by the designer. This section discusses these parameters and how they affect power usage.</p><p&

8、gt;　　Reducing System Clock Frequency</p><p>　　In CMOS digital logic devices, power consumption is directly proportional to system clock (SYSCLK) frequency: power=CV2?, where C is CMOS load capacitance, V is

9、supply voltage, and ? is SYSCLK frequency.</p><p>　　Equation 1.CMOS Power Equation</p><p>　　The system clock on the C8051Fxxx family of devices can be derived from an internal oscillator or an e

10、xternal source. External sources may be a CMOS clock, RC circuit, capacitor, or crystal oscillator. For information on configuring oscillators, see application note: “AN02 - Configuring the Internal and External Oscillat

11、ors.” The internal oscillator can provide four SYSCLK frequencies: 2, 4, 8, and16 MHz. Many different frequencies can be achieved using the external oscillator.</p><p>　　To conserve power, a designer must de

12、cide what the fastest needed SYSCLK frequency and required accuracy is for a given application. A design may require a constant SYSCLK frequency during all device operations. In this case, the designer will choose the lo

13、west possible frequency required, and use the oscillator configuration that consumes the least power. Typical applications include serial communications, and periodic sampling with an ADC that must be performed. </p&g

14、t;<p>　　Some operations may require high speed operation, but only in short, intermittent intervals. This is sometimes referred to as “burst” operation. In the C8051Fxxx, the SYSCLK frequency can be changed at any

15、time. Thus, the device can operate at low frequency until a condition occurs that requires high frequency operation.</p><p>　　Two examples of alternating between SYSCLK sources are (1) an internal oscillator

16、/external crystal configuration, and (2) an external crystal/RC oscillator configuration. If the device is used for occasional high speed data conversion, and a real-time clock is used for time-stamping the data, a combi

17、nation internal oscillator and external crystal would be ideal. During sampling operations, the high speed internal oscillator would be used. When sampling is complete, the device could then use an e</p><p>

18、　　The crystal oscillator and internal oscillator may be operated simultaneously and each selected as the SYSCLK source in software as desired. To reduce supply current, the crystal may also be shutdown when using the int

19、ernal oscillator. In this case, when switching from the internal to external oscillator the designer must consider the start-up delay when switching the SYSCLK source. The C8051F0xx devices have a flag that is set when t

20、he external clock signal is valid (XTLVLD bit in the OSCXCN re</p><p>　　Some applications require intermittent high speed and accuracy (e.g., ADC sampling and data processing), but have lower frequency and a

21、ccuracy requirements at other times (e.g., waiting for sampling interval), a combination of an external oscillator and RC circuit can be useful. In this case, the external RC oscillator is used to derive the lower freque

22、ncy SYSCLK source, and the crystal is used for high frequency operations. The RC circuit requires a connection to VDD (voltage source) to operate</p><p>　　Because this connection could load the crystal oscil

23、lator circuit while the crystal is in operation, we connect the RC circuit to a general purpose port pin (see Figure 2 below). When the RC circuit is in use, the port pin connection is driven high (to VDD) by selecting i

24、ts output mode to “push-pull” and writing a ‘1’ to the port latch. When the crystal oscillator is being used, the port pin is placed in a ‘hi- Z’ condition by configuring the output mode of the port to “open-drain” and w

25、riting a</p><p>　　The start-up of the RC-circuit oscillator is nearly instantaneous. However, there is a notable start-up time for the crystal. Therefore, switching from the RC oscillator to the external cry

26、stal oscillator using the following procedure:</p><p>　　1. Switch to the internal oscillator.</p><p>　　2. Configure the port pin used for the RC circuit voltage supply as open-drain and write a

27、‘1’ to the port pin (Hi-Z condition).</p><p>　　3. Start the crystal (Set the XFCN bits).</p><p>　　4. Wait for 1 ms.</p><p>　　5. Poll for the External Crystal Valid Bit (XTLVLD -->

28、; ‘1’).</p><p>　　6. Switch to the external oscillator.</p><p>　　Switch from the external crystal oscillator to the RC oscillator as follows:</p><p>　　1. Switch to the internal oscil

29、lator.</p><p>　　2. Shutdown the crystal (clear the XFCN bits).</p><p>　　3. Drive the voltage supply port pin high (to VDD) by putting the port pin in “push pull” mode and writing a ‘1’ to its po

30、rt latch.</p><p>　　4. Switch back to the external oscillator.</p><p>　　Supply Voltage</p><p>　　The amount of current used in CMOS logic is directly proportional to the voltage of th

31、e power supply. The power consumed by CMOS logic is proportional the power supply voltage squared (See Equation 1). Thus, power consumption may be reduced by lowering the supply voltage to the device. The C8051Fxxx famil

32、ies of devices require a supply voltage of 2.7-3.6 Volts. Thus, to save power, it is recommended to use a 3.0 volt regulator instead of a 3.3 volt regulator for power savings.</p><p>　　CIP-51 Processor Power

33、 Management Modes</p><p>　　The C8051 processor has two modes which can be used for power management. These modes are IDLE and STOP.</p><p><b>　　IDLE Mode</b></p><p>　　In

34、 IDLE Mode, the CPU and FLASH memory are taken off-line. All peripherals external to the CPU remain active, including the internal clocks. The CPU exits IDLE Mode when an enabled interrupt or reset occurs. The CPU is pla

35、ced in IDLE Mode by setting the Idle Mode Select Bit (PCON.0) to ‘1’.</p><p>　　When the IDLE Mode Select Bit is set to ‘1’, the CPU enters IDLE Mode once the instruction that sets the bit has executed. An as

36、serted interrupt will clear the IDLE Mode Select Bit and the CPU will vector to service the interrupt. After a return from interrupt (RETI), the CPU will return to the next instruction following the one that had set the

37、IDLE Mode Select Bit. If a reset occurs while in IDLE Mode, the normal reset sequence will occur and the CPU will begin executing code at memory locatio</p><p>　　As an example, the CPU can be placed in IDLE

38、while waiting for a Timer 2 overflow to</p><p>　　Initiate a sample/conversion in the ADC. Once the conversion and sample processing is complete, the ADC end-of-conversion interrupt wakes the CPU from IDLE Mo

39、de and processes the sample. After the sample processing is complete, the CPU is placed back into IDLE Mode to save power while waiting for the next interrupt.</p><p>　　As another example, the CPU may wait i

40、n IDLE Mode to save power until an external</p><p>　　Interrupt signal is used to “wake up” the CPU as needed. Upon receiving an external interrupt, the CPU will exit IDLE Mode and vector to the corresponding

41、 interrupt vector (e.g., / INT0 or /INT1).</p><p><b>　　STOP Mode</b></p><p>　　The C8051 STOP Mode is used to shut down the CPU and oscillators. This will effectively shut down all di

42、gital peripherals as well. All analog peripherals must be shutdown by software prior to entering STOP Mode. The processor exits STOP Mode only by an internal or external reset. Thus, STOP Mode saves power by reducing the

43、 SYSCLK frequency to zero.</p><p>　　Note that the Missing Clock Detector will cause an internal reset (if enabled) that will terminate STOP Mode. Thus, the Missing Clock Detector should be disabled prior to

44、entering STOP Mode if the CPU is to be in STOP Mode longer than the Missing Clock Detector timeout (100 μs).</p><p>　　The C8051 processor is placed in STOP Mode by setting the STOP Mode Select Bit (PCON.1) t

45、o ‘1’. Upon reset, the CPU performs the normal reset sequence and begins executing code at 0x0000. Any valid RESET source will exit STOP Mode. Sources of reset to exit STOP Mode are External Reset (/RST), Missing Clock D

46、etector, Comparator 0, and the External ADC Convert Start (/CNVSTR).</p><p>　　As an example, the CPU may be placed in STOP Mode for a period to save power when no device operation is required. When the devic

47、e is needed, Comparator 0 reset could be used to “wake up” the device.</p><p>　　Generally, a power conscious design will use the lowest voltage supply, lowest SYSCLK frequency, and will use Power Management

48、Modes when possible to maximize power savings. Most of these can be implemented or controlled in software.</p><p>　　Calculating Power Consumption</p><p>　　There are two components of power consu

49、mption in Cygnet’s C8051F00x and C8051F01x family of devices: analog and digital. The analog component of power consumption is nearly constant for all SYSCLK frequencies. The digital component of power consumption change

50、s considerably with SYSCLK frequency. The digital and analog components are added to determine the total power consumption.</p><p>　　The current use calculations presented in this application note apply to t

51、he C8051F00x and C8051F01x (‘F000, 01, 02, 03, 05, 06, 10, 11, 12, 15, and 16) family of Cygnet devices.</p><p>　　The data sheet section, “Global DC Electrical Characteristics” contains various supply curren

52、t values for different device conditions. The current values are separated into digital (at three example frequencies) and analog components. The analog numbers presented are values with all analog peripherals active. Su

53、pply current values for each analog peripheral can be found in the data sheet section for the peripheral.</p><p>　　For convenience, the Global DC Electrical Characteristics for the C8051F00x and C8051F01x fa

54、mily of devices are presented in the table below.</p><p>　　Internal vs. External Oscillator</p><p>　　Besides using lower SYSCLK frequencies, the designer can realize power savings by making smar

55、t SYSCLK source choices. The internal oscillator will typically consume 200μA of current supplied from the digital power supply. The current used to drive an external oscillator can vary. The drive current (supplied from

56、 the analog power supply) for an external source, such as a crystal, is set in software by configuring the XFCN bits in the External Oscillator Control Register (OSCXCN). Thus, at higher </p><p>　　To minimiz

57、e power consumption, but must be high enough to start the external oscillator. The following table lists the current vs. External Oscillator Frequency Control Bit settings.</p><p>　　Digital Peripherals</p

58、><p>　　For rough calculations, a good rule of thumb is to assume a 1mA/MHz of operating current (digital) + 1mA if the analog components (ADC, comparators, DAC, VREF, etc.) are enabled. This rule of thumb assum

59、es a 3.6 V supply voltage. A lower supply voltage will reduce power consumption. At 2.7 V, the rule of thumb is 0.5mA/MHz (in NORMAL mode). The rules of thumb for rough calculations are presented in the table below:</

60、p><p>　　Analog Peripherals</p><p>　　The individual supply current values for each analog peripheral are posted in the data sheet section for that component (typically near the end of the section).

61、It is recommended to disable all peripherals not in use to save power. For convenience, the C8051F00x and C8051F10x analog peripherals supply current values are listed below:</p><p>　　Calculating Total Curre

62、nt</p><p>　　When the required SYSCLK frequency, supply voltage, and peripherals have been determined, the total supply current can be estimated. To calculate the total supply current, the analog peripheral c

63、urrent use (found by adding the currents of each of the enabled analog peripherals) is added to the digital current use (calculated for a given frequency, power mode, and supply voltage). If all of the analog peripherals

64、 are enabled, analog current use is about 1mA.</p><p>　　Example Calculations</p><p>　　The following are examples of supply current calculations. Each application may use different power modes, S

65、YSCLK frequencies, and peripherals at different times. Thus, power management specifications may require several different supply current calculations. The digital component and analog components of current use are found

66、 separately, and then added together for the total.</p><p><b>　　Example 1</b></p><p>　　The C8051F000 device is being used in a system with VDD=3.6 V. An ADC is sampling parameters an

67、d processing the sample for an output to one DAC. Because of the sampling and processing requirements of the application, SYSCLK frequency is 16 MHz using the internal oscillator.</p><p>　　Analog Components&

68、lt;/p><p>　　Peripheral Supply Current (μ A)</p><p><b>　　ADC 450</b></p><p>　　VREF (internal) 50</p><p>　　Internal Oscan. 200</p><p>　　One DAC 110&

69、lt;/p><p>　　VDD monitor 15</p><p>　　Total Analog 825</p><p>　　Digital Component</p><p>　　In NORMAL Mode @ 16 MHz;</p><p>　　1mA/M Hz * 16 MHz = 16mA</p>

70、<p><b>　　Total</b></p><p>　　825μA (analog) + 16mA (digital)= 16.8mA</p><p><b>　　Example 2</b></p><p>　　Assume we are still estimating the supply curren

71、t in the same application in Example 1. If the sample processing is a burst operation (i.e., intermittent need for sampling and conversions), we may choose to place the CIP-51 in IDLE Mode to allow a Timer to wake-up the

72、 CIP-51 after a specified interval. In this case, the average supply current can be calculated in order to estimate power requirements. The device will switch between NORMAL Mode (for sampling and data conversion) and ID

73、LE Mode (bet</p><p>　　Analog Component</p><p>　　Analog peripherals are disabled during the IDLE Mode period between sample processing and output. Thus, analog current consumption is just:</p&

74、gt;<p>　　VDD monitor = 15μA.</p><p>　　Digital Component</p><p>　　In IDLE Mode @ 16 MHz;</p><p>　　0.65mA/MHz * 16 MHz = 10.4mA</p><p><b>　　Total</b>&l

75、t;/p><p>　　The analog component would be considered negligible in most applications, thus, the total is just the digital component:</p><p>　　50μA (analog) + 10.4mA (digital) = 10.4mA</p><

76、;p>　　Now that we have calculated IDLE Mode supply current and NORMAL Mode supply current (in Example 1), we must calculate the time we spend in each mode to find the average current the device will use.</p><

77、;p>　　Assuming the ADC is in low-power tracking mode and at the maximum SAR conversion</p><p>　　Clock of 2 MHz (ADC set for SAR clock = SYSCLK/8), and we desire a 10 kHz sampling rate. The period of the po

78、wer cycle in Figure 3 is 1/10,000 (sample rate) = 100μs.</p><p>　　The time in NORMAL Mode will be the ADC tracking/conversion time, and the time to store the value in memory. In low-power tracking mode, it w

79、ill take 3 SAR clocks for tracking, and 16 SAR clocks for conversion. 19 SAR clocks at 2 MHz will take 9.5μs. To store the number will take to system clock cycles, or 0.125μs. To enter NORMAL Mode, a move instruction is

80、executed, taking 3 SYSCLK cycles which takes 0.188μs. Thus, the total time in NORMAL Mode is 9.5 μs+0.125 μs+0.188μs = 9.8μs.</p><p>　　Because the ADC sample period is 100μs, the time we may be in IDLE Mode

81、during the power cycle is 100μs - 9.8μs (time in NORMAL Mode) = 90.2μs. By integrating the area under the curve in Figure 3 for one period (100μs), and dividing that number by the　period, the average supply current is 11

82、mA.</p><p><b>　　Example 3</b></p><p>　　If the oscillator frequency were lowered while in IDLE Mode (in Example 2) to 32 kHz using an external crystal for additional power savings, th

83、e current use would be: </p><p>　　The external oscillator control bits will be set to XFCN = 000. This uses 0.6μA of analog current. (0.65mA *.032 MHz) + 0.6μA = 21μA</p><p>　　This is a dramatic

84、 difference from Example 2’s IDLE Mode at 16 MHz, by simply reducing oscillator frequency.</p><p>　　Continuing with the average supply current calculation in Example 2 (with 6 extra SYSCLK cycles in NORMAL M

85、ode to lower the frequency), the average supply current would be 1.7mA!</p><p><b>　　Example 4</b></p><p>　　In this application, the C8051F000 is being used to sample a parameter usin

86、g the ADC and store samples in memory, with high accuracy timing of samples required. For more accurate timing, the SYSCLK is derived from an external 18.432 MHz crystal oscillator. To save power, the designer has decide

87、d to use a supply voltage of 3.0 V. Timer 2 is used to time the ADC sampling intervals.</p><p>　　Digital Component</p><p>　　In NORMAL Mode @ 18.432 MHz;</p><p>　　0.8mA/MHz * 18.432

88、MHz = 14.7mA</p><p>　　Total Current Use</p><p>　　3.4mA (analog)+14.7mA (digital)= 18.1mA</p><p>　　Example 4 in IDLE Mode</p><p>　　Placing the application in IDLE Mode w

89、ith the ADC disabled during intervals that sampling is not required (no CIP-51 operations are needed; digital peripherals continue to operate) will save power if the sampling operation is a burst operation. In IDLE Mode,

90、 the digital current consumption is only 0.6mA/MHz, with no ADC, thus the current consumption at 18.432 MHz =11.1 miscalculating the average supply current for one sample period (similarly to Example 2, assuming a 10 kHz

91、 sampling rate and low</p><p>　　附錄4 英文資料翻譯</p><p><b>　　電源管理技術(shù)及計(jì)算</b></p><p>　　本設(shè)計(jì)應(yīng)用于下列器件 </p><p>　　C8051F000、C8051F001、C8051F002、C8051F005、C8051F006、C8051F

92、010、C8051F011、C8051F012、C8051F015、C8051F016、C8051F017 </p><p><b>　　1　引言</b></p><p>　　本應(yīng)用筆記討論電源管理技術(shù)及計(jì)算C8051F00x和C8051F01x Sock中的功率消耗的方法。很多應(yīng)用系統(tǒng)對(duì)功耗有嚴(yán)格的要求，也存在幾種不以犧牲性能為代價(jià)的降低功耗的方法，計(jì)算預(yù)計(jì)功耗對(duì)于

93、說(shuō)明系統(tǒng)的供電要求是很重要的 。</p><p><b>　　2　關(guān)鍵點(diǎn)</b></p><p>　　供電電壓和系統(tǒng)時(shí)鐘頻率對(duì)功率消耗有很大影響 。</p><p>　　Cygnet的Sock有兩種電源管理方式等待和停止。 </p><p>　　功率消耗可以作為系統(tǒng)時(shí)鐘電源電壓和被允許的外設(shè)的函數(shù)來(lái)計(jì)算。 </p&

94、gt;<p><b>　　3　降低功耗的方法</b></p><p>　　CMOS數(shù)字邏輯器件的功耗受供電電壓和系統(tǒng)時(shí)鐘（SYSCLK）頻率的影響?？梢酝ㄟ^(guò)調(diào)整這些參數(shù)來(lái)降低功耗，設(shè)計(jì)者也很容易控制這些參數(shù)。本節(jié)討論這些參數(shù)及它們對(duì)功率消耗的影響 。</p><p>　　4　降低系統(tǒng)時(shí)鐘頻率</p><p>　　在CMOS數(shù)字邏輯

95、器件中，功耗與系統(tǒng)時(shí)鐘（SYSCLK）頻率成正比： </p><p><b>　　功耗 = CV2f</b></p><p>　　其中C是CMOS的負(fù)載電容，V是電源電壓，f是SYSCLK的頻率 。</p><p>　　C8051Fxxx系列器件的系統(tǒng)時(shí)鐘可以來(lái)自?xún)?nèi)部振蕩器或一個(gè)外部時(shí)鐘源。外部源可以是一個(gè)CMOS時(shí)鐘、RC電路、電容或晶體振蕩

96、器。有關(guān)振蕩器配置方面的信息見(jiàn)應(yīng)用筆記–“ 配置內(nèi)部和外部振蕩器”。內(nèi)部振蕩器可提供四個(gè)時(shí)鐘頻率2、4、8 和16 MHz。很多不同的頻率可以通過(guò)使用外部振蕩器得到，為了節(jié)省功耗設(shè)計(jì)者必須知道給定應(yīng)用所需要的最高SYSCLK頻率和精度。一個(gè)設(shè)計(jì)可能需要一個(gè)在器件全部工作時(shí)間內(nèi)保持不變的SYSCLK頻率。在這種情況下，設(shè)計(jì)者將選擇滿足要求的最低頻率，采用消耗最低功率的振蕩器配置。典型的應(yīng)用包括串行通信和必須用ADC完成的周期性采樣。<

97、;/p><p>　　某些操作可能要求高速度，但只是在很短的、斷續(xù)的時(shí)間間隔內(nèi)。這種情況在某些時(shí)候被稱(chēng)為“猝發(fā)”操作。在C8051Fxxx中，SYSCLK頻率可在任何時(shí)刻改變，因此器件平時(shí)可工作在較低的頻率，直到某個(gè)需要高速操作的條件發(fā)生。</p><p>　　切換系統(tǒng)時(shí)鐘源的兩個(gè)例子是（1）內(nèi)部振蕩器/外部晶體配置，（2）外部晶體/RC振蕩器配置。如果器件偶爾進(jìn)行高速數(shù)據(jù)轉(zhuǎn)換，并使用一個(gè)實(shí)時(shí)時(shí)

98、鐘為數(shù)據(jù)提供時(shí)間戳，則一個(gè)內(nèi)部振蕩器和外部晶體的組合將是最理想的。在采樣操作期間應(yīng)使用高速內(nèi)部振蕩器。采樣結(jié)束后，使用一個(gè)外部32kHz晶體以維持實(shí)時(shí)時(shí)鐘。一旦重新需要高速操作，器件將切換到內(nèi)部振蕩器（見(jiàn)圖1）。在應(yīng)用筆記“ 實(shí)現(xiàn)一個(gè)實(shí)時(shí)時(shí)鐘”中給出了這種操作過(guò)程的一個(gè)例子。 </p><p>　　圖1. 內(nèi)部振蕩器和外部晶體源配置</p><p>　　晶體振蕩器和內(nèi)部振蕩器可以同時(shí)工作，

99、每一個(gè)都可以根據(jù)需要被選為系統(tǒng)時(shí)鐘源。為了減小電源電流，在使用內(nèi)部振蕩器時(shí)可停止晶體振蕩器。在這種情況下，當(dāng)從內(nèi)部切換到外部振蕩器時(shí)，設(shè)計(jì)者必須考慮切換系統(tǒng)時(shí)鐘源時(shí)的起動(dòng)延遲。C8051F0xx器件有一個(gè)指示外部時(shí)鐘信號(hào)有效的標(biāo)志位（OSCXCN寄存器中的XTLVLD位），該標(biāo)志在外部振蕩器穩(wěn)定運(yùn)行時(shí)置位。在切換到外部振蕩器之前應(yīng)查詢(xún)?cè)摌?biāo)志。注意：在外部晶體起動(dòng)期間，其它操作可繼續(xù)使用內(nèi)部振蕩器。</p><p>

100、;　　某些應(yīng)用需要間歇的高速度和高精度（例如ADC采樣和數(shù)據(jù)處理），但在其它時(shí)間可允許低速度和低精度（例如等待采樣時(shí)），這時(shí)可以用到外部振蕩器和RC電路的組合。在這種情況下，外部RC振蕩器用于產(chǎn)生低頻SYSCLK源，而晶體用于高頻率操作。RC電路需要接到VDD（電壓源）才能工作。由于在晶體處于工作狀態(tài)時(shí)，這種連接可能加載晶體振蕩器電路，我們將RC電路接到一個(gè)通用端口引腳（見(jiàn)圖2），當(dāng)使用RC電路時(shí)，與之連接的端口引腳被驅(qū)動(dòng)到高電平（到V

101、DD），這可以通過(guò)選擇端口為“推挽”輸出方式并向端口鎖存器寫(xiě)“1”來(lái)實(shí)現(xiàn)。當(dāng)使用晶體振蕩器時(shí)，端口引腳被置于“高阻”狀態(tài)，這是通過(guò)設(shè)置端口為“漏極開(kāi)路”輸出方式，并向端口鎖存器寫(xiě)“1”來(lái)實(shí)現(xiàn)的。注意：RC電路可以利用晶體振蕩器電路中已有的電容 。</p><p>　　RC電路振蕩器的起動(dòng)幾乎是瞬間完成的，然而晶體振蕩器的起動(dòng)時(shí)間是比較可觀的。因此從RC振蕩器切換到外部晶體振蕩器時(shí)要經(jīng)過(guò)下列過(guò)程 ：</p&g