畢業(yè)設(shè)計(jì)外文翻譯--基于c51兼容微處理器單片機(jī)的pwm控制器設(shè)計(jì)

1、外文翻譯1附錄 附錄 A 英文原文 英文原文Design of PWM Controller in a MCS-51 Compatible MCUAuthor . Yue-Li Hu, Wei Wang Microelectronic Research & Development CenterCampus P.O.B.221, 149 Yanchang Rd, Shanghai 200072, China Introduct

2、ionPWM technology is a kind of voltage regulation method by controlling the switch frequency of DC power with fixed voltage to modify the two-end voltage of load. This technology can be used for a variety of applications

3、 including motor control, temperature control and pressure control and so on. In the motor control system shown as Fig. 1, through adjusting the duty cycle of power switch, the speed of motor can be controlled. As shown

4、in Fig. 2, under the control of PWM signal, the average of voltage that controls the speed of motor changes with Duty-cycle ( D = t1/T in this Figure ), thus the motor speed can be increased when motor power turn on, dec

5、reased when power turn off.Fig.1: The Relationship between Voltage of Armature and Fig.2 Architecture of PWM ModuleTherefore, the motor speed can be controlled with regularly adjusting the time of turn-on and tu

6、rn-off. There are three methods could achieve the adjustment of duty cycle: (1) Adjust frequency with fixed pulse-width. (2) Adjust both frequency and pulse-width. (3) Adjust pulse-width with fixed frequency. Generally,

7、there are four methods to generate the PWM signals as the following: (1) Generated by the device composed of separate logic components. This method is the original method which now has been discarded. (2) Generated by so

8、ftware. This method need CPU to 外文翻譯3? Duty cycle updates are configurable to be immediated or synchronized to the PWMFig.3 Architecture of PWM ModuleDetails of the architecturePMW generatorThe architecture of the 2-outp

9、ut PWM generator shown in Fig.4 is based on a 16-bit resolution counter which creates a pulse-width modulated signal. The system is synthesized by a system clock signal whose frequency can be divided by 4 times or 12 tim

10、es through setting the value of T3M for PWM0 or T4M for PWM1 in the special register PWMCON as shown in Fig.4. To PWM0 generator, the clock to 16-bit counter will be pre-divided by 4 times by default when T3M is set to z