基于概率的rtl模塊功耗估算方法

1、1AfastRTLPowerEstimatfCombinationalCircuit1一種快速的組合電路一種快速的組合電路RTL功耗估算器功耗估算器ZHAOWenqing(趙文慶)CUIMingdong(崔銘棟)TANGPushan(唐璞山)(CADLabElectronicEngineeringDepartmentFudanUniversity200433Shanghai)復(fù)旦大學(xué)電子工程系復(fù)旦大學(xué)電子工程系CAD研究室，研究室，20

2、0433，上海，上海Abstract：VLSIdesignistowardmuchhigherlevelwiththedevelopmentofmodernsynthesistools.Howeverduetothecomputationalcomplexityproblemgatelevelpowerestimatsarebecomingmemeinapplicablefhighlevelmodules.Indertoestimate

3、circuitpowerattheearlydesignstageRTLpoweranalysistoolsareneeded.InthispaperwepresentafastmethodtocalculateRTLcombinationalmodulepower.Oncethepowerlibraryisbuiltwecangivethepowerdissipationofacertainmoduleunderstimulation

4、ofanyinputvect.OurmethodusedTayl’sexpansiontoestablishanequationbasedmodelMonteCarlosimulationisusedflibraryestablishment.TheresultofISCAS85benchmarkshowsthattherelativeerrofourmethodiswithin5%.Keywds:RTLpoweranalysis摘要：

5、摘要：隨著現(xiàn)代綜合工具的發(fā)展，集成電路設(shè)計(jì)越來(lái)越趨向于更高的層次。門(mén)級(jí)的功耗模擬器由于在計(jì)算復(fù)雜度上存在的問(wèn)題，對(duì)于高層次模塊變得愈加不適用。為了設(shè)計(jì)初期能在高層次進(jìn)行功耗估算，我們需要RTL的功耗模擬器。本文提出了一種快速分析組合RTL模塊功耗的方法，經(jīng)過(guò)建立模塊功耗庫(kù)，可以非?？斓挠?jì)算出任意輸入向量驅(qū)動(dòng)的電路功耗。我們的方法使用泰勒一階近似的公式模型，并在建庫(kù)過(guò)程中采用MonteCarlo模擬方法。ISCAS85benchmark電

6、路模擬的結(jié)果顯示，該方法的誤差可以在5％以?xún)?nèi)。關(guān)鍵字：關(guān)鍵字：RTL，功耗分析1.IntroductionItistypicallythecasethatareaspeedreliabilityarealwaysgivenmeconcernintraditionalICdesignprocesshowevermuchlargerscalemuchfasterspeedofmodernelectronicsystemshasledtoas

7、eriousofpowerrelatedproblemswhicharereceivingmeconcern.Oftengeneralpurposemacrosdevelopedindependentlybythirdpartyintellectualproperty(IP)providersarereusedeverywhere.Inapowerconstraintdesign(suchasconsumerelectronicdevi

8、ces)thepowerdissipationofhighlevelmodulesarerequiredtobepredictedatearlydesignphase.Thustoolsthatallowdesignertoevaluatepowerbudgetduringvariousdesignphasesareingreatdems.Researchongatelevelpowerestimathasbeenonfquitealo

9、ngtimemanytechniqueshavebeenproposed(paper[1]givesasurvey).Practicaltoolsarealreadyinusenow.Theseestimatscangiveprecisepowerdissipationofacircuitdrivenbycertaininputvects.Howeverduetothenatureofitssimulationprocessgatele

10、velestimatsalwayshavetheslowestspeedmecriticaldisadvantageisthatcircuitlistmustbeknownbefeanysimulationcouldbeperfmedthisgreatlyblockedtheadvanceofhighleveldesigntechnology.DesignersarenolongersatisfiedwithsuchestimatsaR

11、TLestimatwhichwillhelpthemtocrectlyevaluate1ThisresearchissupptedbyNationalHighTechnologyResearchDevelopment863Plan863SOCY33NSFCoversea’syoungscientistjointresearchproject69928402thedoctalprogramfoundationofMinistryofEdu

12、cationofChina2000024628NSFCproject69806004foundationfuniversitykeyteacherbytheMinistryofEducation本文工作受?chē)?guó)家863計(jì)劃863－SOC－Y－2－6－1，863－SOC－Y－3－3，國(guó)家自然科學(xué)基金海外杰出青年學(xué)者合作研究基金項(xiàng)目69928402，國(guó)家自然科學(xué)基金項(xiàng)目69806004，教育部高等學(xué)校博士學(xué)科點(diǎn)專(zhuān)項(xiàng)科研基金2000024628和

13、教育部高等學(xué)校骨干教師資助計(jì)劃資助3powerisasfollows：)1(5.002???miiavgieffdynamicECVPinwhichVisoperatingvoltage，Cieffiseffectivecapacitanceonnodei.，Eiavgistheaveragetransitionprobabilityofnodei.Staticpower4)ismainlydeterminedbycircuitscal

14、eprocesswhichcanbedescribedbyafunctiondirectlyproptionaltothecircuitscale.PracticallyspeakingtheRTLsimulatsproblemsareblackboxproblemsi.e.theinnerstructureofeachmoduleistransparenttousersnomatterthemoduleisahardmodulewhi

15、chcontainslowlevelgatestructureinterconnectioninfmationasoftmodulewhichcontainsonlyVHDLcode.Inthecaseofsoftmodulesthereisnoguaranteethatthefinalimplementationisexactlythesameastheoneinourpowerlibraryfdifferentsynthesisto

16、olswillgeneratedifferentimplementation.Ifwesticktothemoduleinourlibraryerrswillbeinevitable.Ftunately[9]haspointedthatmismatchesinfinalimplementationproducedbytechnologylibrarysynthesistoolstendtohavelimitedvariancealtho

17、ughtheirabsolutevaluecanbesignificant.LibrarybasedonacertaintechnologycanbeeasilymodifiedtoadaptothertechnologiesonlyatechnologyscalingparameterStechisneededtomakethismodification.Technologytuningisperfmedoncefall.Wemana

18、getobuildaninnerstructureirrelevantmodelthismodelusesthesamemethodtohledifferentkindsofRTLmodulefgeneralpurpose.Theonlyinfmationwecangettoevaluateasystemleveldesignismodulelistitsinterconnection.Afterbehaviallevelsimulat

19、iontheinputoutputvectsofeachmoduleareknownsoathoughstudyofvectsisessentialtofinditscontributiontomodulepowerdissipationthiswillbediscussedlaterinthisSection.2.2InputvectpropertyOfteninRTLpoweranalysisaveragesignalprobabi

20、lityPavgaveragesignaltransitiondensityDavgareused[7].Takeacircuitmodulewithminputptsasaexample.FasingleinputptwithinputsV=[v1…vn]vxequalsto01wedefinesignalprobabilityPisignaltransitiondensityDi:)1.(11111defnVVDnVPnjjjinj

21、ji??????????ObviouslyPistheproptionoflogicalhighinnvectcycleswhileDistheproptionofsignaltransitioninn1adjacentvectcycles.ThenPavgDavgaredefinedas：)2.()1(111111defnmVVDmnVPminjjjavgminjjavg??????????????thetwoparametersar

22、enotindependenttheconstraintbetweenthemasfollows：)2(212DPD???StatisticallyPisafunctionofDthegraphofthisfunctionissomethinglikeareversedbellsowefocusonparameterDbelievethattheeffectofPcouldbereflectedindirectly.2.3Erreval

23、uationToevaluatetheaccuracyofourRTLmodelweintroducetwoerrfacts:averagerelativeerrREavgaveragetotalerrTEavg.alsowedefinemaxrelativeerrEmax)3.(11max1111defxExExEMAXExExExETExExExEpREiiipipiipiipiiavgpiiiiavg???????????????