片上高速緩存及內(nèi)存管理宏單元設計.pdf

1、東南大學碩士學位論文片上高速緩存及內(nèi)存管理宏單元設計姓名：凌青申請學位級別：碩士專業(yè)：微電子與固體電子指導教師：胡晨20060316AbstraetThcmostdittieultyoftoday’sSoCacsigistilelargeditfereneebetweenthelowspeedofcxtemalmemory’saocc輜andtlaehighspccdoftheembeddedplroccssorThedifferenc

2、elimitsthelcrfor啪ceoftlaccmbeddedprocessorIntherecentyearstlaedifferenceisbceomi蜉largerandlargcrasitiscalled“MemoryGapbytheengineerReeently也e∞malotofmethodsteAueethespccdgap，oncofthcmosteffeetivemethodistointegratetlaeCa

3、elae柚dMMUmodulcontothe$oCchipAsaresultaesigaCaelaeandMMUmodulewiltlhighparformaccisveryimportantTllis粥takestlacCrarfield5systemchip∞r(nóng)esearchobj∞twlaichisdesignbyASIC蚴arelacenterinSoutheastOniversitythemaintaskistoacsignC

4、ad磚andMMUmodulebasedontheARM7TDMIcoreinthecllipBeginningfromtileintroductionofmodule’sprineiple’wefullyeomider血ceffectofareaandpOWClr鋤d曲時applicationrequirementofthesystemehiptoi蜘lnethedesignfactor觚dcircuitstructllaeThenw

5、ecompletethedesignofthemacromoduleandthecontrollogicofthemoduleAtlastthesimulatioandtestworkisIcreormedWeu∞fullcIntommethodtodesigntlaemacromoduleespeciallytotlae$RAMmemoryc211Itisbecametlaespendingofamandpowerofthe$RAMm

6、orycelltakesalotofpeeentageofthewholemacromodules’UsingtlaeaexponentMOSFETmodeltesultthewordlinc、bitlinepowermodelandactaymodeltogetherwiththealcamodelandanalysisoftheread／Mritcreliabilitywebringoutamelllodtooptimizethem

7、emorycell如devaluatethepcformanccoftheresultTheoptnnizcdceilIresnotonlyreducedthepower、delayandareabutalsostrengthenedlheantinoiseabilityImplem蚰tedinSMICo18pmCMO$processwitla18Vsupplyvoltagethea嘲ofthemodulej8312ramz(toget

8、herwith血cARM7TDMIcore)CPIis119powcris332row(under120MHz’sCPU丘“I啪cy)TheMPWresultshowsthat：theCacheandMMUmodulehavegoodftmetionbuttheCPIJ蕾requ粕ccc趾onlyreaclaIOOMHzwcanalysisthe“sonindetailandbringoutaresolvemetlaodKeyWords