vhdl語言設(shè)計(jì)數(shù)字系統(tǒng)的外文翻譯

1、<p>　　Designing a Digital system with VHDL </p><p>　　Valentina Stoyanova Kukenska</p><p>　　Abstract: In this paper a digital system designing with VHDL is presented. Here are exposed sequen

2、tially all the phases of the very digital system's designing. The main methods are also on show here. The project descriptions’ types are presented. The stress is put on the use of VHDL for synthesis of structural an

3、d behavioral models.</p><p>　　For creating the project of the chosen digital system an integrated system WebPack was used, as well as ModelSIm XE II for the model's simulation. </p><p>　　Key

4、words: Design, VHDL, digital systems, model, WebPack </p><p>　　1. INTRODUCTION</p><p>　　The digital systems are complex ones, consisting of lots of components. As far as the automated design o

5、f such systems is concerned, methods for designing time reducing and limiting the complexity of the task are sought out and applied. A method of the kind is connected with the decomposition and hierarchy principles. The

6、decomposition of the systems is realized in a way, which differentiates functionally independent modules. </p><p>　　A digital system can be described as a module with inputs and/or outputs. The electrical va

7、lues on the outputs are some function of the values on the inputs. </p><p>　　One way of describing the function of a module is to describe how it is composed of sub-modules. Each of the sub-modules is an ins

8、tance of some entity, and the ports of the instances are connected using signals. This kind of description is called a structural description.</p><p>　　In many cases, it is not appropriate to describe a modu

9、le structurally. One such case is a module, which is at the bottom of the hierarchy of some other structural description. For example, if you are designing a system using IC packages bought from an IC shop, you do not ne

10、ed to describe the internal structure of an IC. In such cases, a description of the function performed by the module is required, without reference to its actual internal structure. Such a description is called a functio

11、nal o</p><p>　　Usually, for structural and behavioral description, either Verilog or VHDL is used. In this paper a designing with VHDL is presented. Here are exposed sequentially all the phases of the very d

12、igital system's designing. The main methods are also on show here. The project descriptions’ types are presented. The stress is put on the use of VHDL for synthesis of structural and behavioral models. Here are prese

13、nted several VHDL models of computer systems’ components. </p><p>　　2. Methods and stages in digital systems’ design</p><p>　　In digital systems’ design, as well as design of complex systems, a

14、couple of methods are in use:</p><p>　　?        top - down designing;</p><p>　　?        up - down designing.</p><

15、p>　　In top - down designing the building up of the system is usually started from below in upright direction through elaborating the element blocks’ schemes, assembled later to form the whole product.</p><p

16、>　　An advantage of this method is the use of representation on functional block level and the lower, the structural level, is addressed only during the error check simulations within the project.</p><p>　

17、　The up-down designing starts with a specification on the highest level. After that, the project is being decomposed into functional blocks and the requirements for the income and outcome time proportions are specified.

18、The functional models are described through behavioral models or by models on register levels and are subsequently simulated.</p><p>　　Some of the advantages of the methods are: </p><p>　　? 

19、;       аn easier execution of the task’s specifications;</p><p>　　?        иt allows a projects’ check on system level, without tackling the

20、structural details;</p><p>　　?        The project’s check is done, with no regard to the technology of its realization. That allows that the choice of technology be made on

21、 a later stage of the designing project.</p><p>　　The most effective up-down designing method is the use of an abstract description of the scheme and the sequential details specifying of the different hierar

22、chy levels’ description. </p><p>　　The digital systems’ design goes through the next stages:</p><p>　　?        Specification;</p><p>　　? 

23、0;      Functional (electrical) designing;</p><p>　　?        Physical designing;</p><p>　　?       

24、Manufacturing;</p><p>　　?        Testing.</p><p>　　Through specification the product parameters, necessary for its proper destination, are determined.</p>

25、;<p>　　Through the functional (electrical) designing, the electrical scheme, responsible for the functions and parameters of the product, in terms of the specification, is elaborated.</p><p>　　The beh

26、avioral stage serves as a description for the scheme as a system, and its entries and exits are marked out. In most of the cases, VHDL models are used.</p><p>　　The Functional (electrical) designing deals wi

27、th main functional blocks’ elaboration. Usually a detailed VHDL description of the functional block is made and being checked by a VHDL simulation.</p><p>　　With the increasing complexity of the projects, fo

28、r the elaboration on structural level, the technique of synthesis is applied. It allows that the scheme with logical elements be synthesized from a VHDL description. Through logical description details such as charging,

29、elements’ delay, are specified and crucial methods and problems with time scattering of signals are defined.</p><p>　　The Physical designing stages strongly depend on technology. The common task is concerned

30、 with the deploying of the logical elements and defining (tracing) their interrelations. </p><p>　　Provided that for the product realization PLD, CPLD or FPGA chips are used, then the result of the physical

31、designing represents a configuration file for designing the chosen device’s resources. </p><p>　　The testing of the project represents a number of procedures, used by designers, to provide:</p><p&

32、gt;　　adequacy between project and specification; </p><p>　　the execution of the project in terms of the chosen technology. </p><p>　　The designing process is usually iterative, including pre-des

33、igning of given parts, until the intended indicators are obtained.</p><p>　　For the tasks of testing in electrical designing (the functionality of the product and its electrical parameters), simulations are

34、used.</p><p>　　The simulation on behavioral level defines how the product will run, before its actual compounding blocks are chosen. For working out of the behavioral models, the hardware description languag

35、es are used (VHDL, Verilog and others).</p><p>　　Through simulation, on a logical primitives level, the schemes are built up with basic logical elements “AND-NO”, “OR-NO”, invertors and triggers and are bein

36、g simulated in order to find out irrelevances with their expected acting.</p><p>　　In functional testing, the delays are not concerned or they are supposed similar for all logical elements.</p><p&

37、gt;　　Error identification after the physical design</p><p>　　After topology’s final elaboration are made the next procedures:</p><p>　　?        check out of th

38、e tech norms throughout manufacturing;</p><p>　　?        check out for the project’s authenticity.</p><p>　　The tech norms for manufacturing are specific for e

39、ach technological process. </p><p>　　The authenticity verification of the project aims to guarantee the product’s proper working. It includes:</p><p>　　?       

40、; finding out the interconnection of the scheme; </p><p>　　?        finding out the parasite components of the topology.</p><p>　　3. Types of design descriptio

41、ns</p><p>　　Through the designing process, three types of design description are in use:</p><p>　　?        behavioral;</p><p>　　?   

42、;     structural;</p><p>　　?        physical.</p><p>　　The behavioral description tackles the system as if it were a kind of “black box” wi

43、th its entrances and exits, with no regard to its structure. The aim is to ignore the redundant details and to concentrate on the specification of the necessary for the functions, which are to be done by the product. On

44、this stage, languages for the apparatus part are used HDL (Hardware Description Languages) - VHDL, Verilog and others. </p><p>　　The structural description defines the way that the system is to be built up.

45、Here, the system’s structure, made of blocks and their interrelations, is tackled. The subsystems, which are to provide its functional execution, as well as their detailed description for analysis of the operational spee

46、d, charging and so on, are defined. The structural description can be presented by languages for the description of the hardware, as well as by electrical schemes.</p><p>　　The design process is connected wi

47、th the transformations of the systems’ descriptions and their sequential details specification. Decomposition from behavioral to structural description can be realized on a number of levels in a hierarchy. From the highe

48、st to the lowest, these levels can be outlined as it follows:</p><p>　　?        system level;</p><p>　　?        functional l

49、evel;</p><p>　　?        logical level;</p><p>　　?        scheme level.</p><p>　　On the highest system level, th

50、e system’s behavior is represented by algorithms that describe its functions. In order that these functions be executed, the architecture of the system is worked out, including microprocessors, memories, main boards and

51、other structural components. </p><p>　　On the lower level, the system’s behavior is described by Bolivia equations. For their execution, logical elements and triggers are used.</p><p>　　4. Use o

52、f VHDL for synthesis of structural and behavioral models</p><p>　　VHDL is a Hardware Description Language for describing digital system [2].</p><p>　　VHDL is designed to full a number of needs i

53、n the design process. </p><p>　　VHDL contains a number of facilities for modifying the state of objects and controlling the flow of execution of modules.</p><p>　　In VHDL, an entity is such a mo

54、dule which may be used as a component in a design, or which may be the top-level module of the design. The entity declarative part may be used to declare items, which are to be used in the implementation of the entity. &

55、lt;/p><p>　　Once an entity has had its interface specified in an entity declaration, one or more implementations of the entity can be described in architecture bodies. Each architecture body can describe a diff

56、erent view of the entity.</p><p>　　The declarations in the architecture body define items that will be used to construct the design description.</p><p>　　Signals are used to connect sub modules

57、in a design. The sub modules in an architecture body can be described as blocks. A block is a unit of module structure, with its own interface, connected to other blocks or ports by signals. A signal assignment schedules

58、 one or more transactions to a signal (or port).</p><p>　　The primary unit of behavioral description in VHDL is the process. When more than one process is activated at the same time, they execute concurrentl

59、y.</p><p>　　A process statement which can be used in an architecture body or block. The declarations define items which can be used locally within the process.</p><p>　　A process may contain a n

60、umber of signal assignment statements for a given signal, which together form a driver for the signal.</p><p>　　VHDL descriptions write them in a design file. After then invoke a compiler to analyze them and

61、 insert them into a design library. A number of VHDL constructs may be separately analyzed for inclusion in a design library. These constructs are called library units. A design file may contain a number of library units

62、.</p><p>　　The behavioral model represents a functional interpretation of the designed digital system. The hardware of the digital device is regarded as a kind of a discreet system. Its behavior is described

63、 as a number of operations. These operations are applied within the system’s database. Within the creation of behavioral VHDL models, operations are described by processes and their interconnections-by signals. On fig 1

64、is presented a VHDL model of a linear decipherer.</p><p>　　library IEEE;</p><p>　　use IEEE.std_logic_1164.all;</p><p>　　entity DESHIF is</p><p>　　port (x1,x2,x3 in: std

65、_logic;</p><p>　　J: out std_logic_vector(0 to 7));</p><p>　　end DESHIF;</p><p>　　arhitecture STRUCTURAL of DESHIF is</p><p>　　component AND3</p><p>　　port

66、(I1,I2,I3: in std_logic;</p><p>　　O1: out std_logic);</p><p>　　end component;</p><p>　　component NOT1 </p><p>　　port (I1: in std_logic;</p><p>　　O1: out st

67、d_logic);</p><p>　　end component;</p><p>　　signal a,b,c: std_logic;</p><p><b>　　begin</b></p><p>　　U1: NOT1 port map (I1=>x1,O1=>a);</p><p&

68、gt;　　U2: NOT1 port map (I1=>x2,O1=>b);</p><p>　　U3: NOT1 port map (I1=>x3,O1=>c);</p><p>　　U4: AND3 port map (I1=>a,I2=>b,I3=>c,O1=>J(0));</p><p>　　U5: AND3

69、port map (I1=>a,I2=>b,I3=>x3,O1=>J(1));</p><p>　　U6: AND3 port map (I1=>a,I2=>x2,I3=>c,O1=>J(2));</p><p>　　U7: AND3 port map (I1=>a,I2=>x2,I3=>x3,O1=>J(3));&l

70、t;/p><p>　　U8: AND3 port map (I1=>x1,I2=>b,I3=>c,O1=>J(4));</p><p>　　U9: AND3 port map (I1=>x1,I2=>b,I3=>x3,O1=>J(5));</p><p>　　U10: AND3 port map (I1=>x1,I2

71、=>x2,I3=>c,O1=>J(6));</p><p>　　U11: AND3 port map (I1=>x1,I2=>x2,I3=>x3,O1=>J(7));</p><p>　　end STRUCTURAL; </p><p>　　architecture DATA_FLOW of DESHIF is</p&

72、gt;<p>　　signal T1,T2,T3: bit;</p><p><b>　　begin</b></p><p>　　T1<= not x1;</p><p>　　T2<= not x2;</p><p>　　T3<= not x3;</p><p>　

73、　F1<=T1 and T2 and T3;</p><p>　　F2<=T1 and T2 and x3;</p><p>　　F3<=T1 and x2 and T3;</p><p>　　F4<=T1 and x2 and x3;</p><p>　　F5<=x1 and T2 and T3;</p&

74、gt;<p>　　F6<=x1 and T2 and x3;</p><p>　　F1<=x1 and x2 and T3;</p><p>　　F1<=x1 and x2 and x3;</p><p>　　end DATA_FLOW; </p><p>　　fig.1 VHDL code of a line

75、ar decipherer</p><p>　　Structural VHDL models are means for reflecting the project’s hierarchy. They are built up by decomposition of digital systems of functionally interconnected parts. These parts are pre

76、sented as components, and their interconnections are realized through signals. These signals enter and exit the components via ports.</p><p>　　For example, within the designing of the digital module, present

77、ed on [2], its structural model has three main components-counter, decoder and light-diode seven-segment display. On fig.2 is shown a part of the structural model, synthesized in WebPack. </p><p>　　Fig.2 . V

78、HDL structural description</p><p>　　The simulation starts with an initialization phase, and then proceeds by repeating a two-stage simulation cycle. In the initialization phase, all signals are given initial

79、 values, the simulation time is set to zero, and each module’s behavior program is executed. This usually results in transactions being scheduled on output signals for some later time.</p><p>　　The purpose o

80、f the simulation is to gather information about the changes in system state over time. This can be done by running the simulation under the control of a simulation monitor. The monitor allows signals and other state info

81、rmation to be viewed or stored in a trace file for later analysis. It may also allow interactive stepping of the simulation process, much like an interactive program debugger.</p><p>　　The computer-synthesiz

82、ed models of the structure and behavior of the digital systems are used for the elaboration of project units. </p><p>　　5. Conclusion</p><p>　　With the increasing complexity of the projects, str

83、uctural presentation on a logical elements’ level, becomes a hard, even impossible. Therefore, a higher abstraction level description would allow optimal results to be reached, such as consummation, characteristics, size

84、 and price. </p><p>　　The hardware description language VHDL is quite suitable for purposes of that kind. It can be used for a high-level behavioral description, as well as for detailed structural descriptio

85、n.</p><p>　　This language provides:</p><p>　　?        a standard way for documenting the project;</p><p>　　?      &#

86、160; means for creation of abstract simulation models, which can be used by each VHDL-simulator;</p><p>　　?        possibility for an automatic synthesis of the electrical

87、scheme from the project’s abstract description.</p><p>　　The VHDL language allows the elaboration of a complete functional structural model of the specialized integral scheme, which can be simulated in order

88、 to assess its adequacy in terms of the specification’s requirements. Thus, a higher quality of the project is guaranteed, because errors and problems are found out shortly after the start of the designing process.</

89、p><p>　　6. References</p><p>　　[1]. Lipsett R., C. Ussery, VHDL: Hardware Description and Design, 1989.</p><p>　　[2]. Kukenska V., I. Simeonov, Designing of a Digital module for Manage

90、ment of a Seven-segmented indication with Programming logics through the use of the Description language VHDL, The 12 International Scientific and Applied Science Conference, ELECTRONICS ET'2002, Sozopol, Bulgaria, S

91、eptember 25-27, 2003. </p><p>　　[3]. Navabi Z. , VHDL: Analysis and Modeling of Digital Systems, McGraw-Hill, 1993.</p><p>　　用 VHDL 實(shí)現(xiàn)數(shù)字系統(tǒng)的設(shè)計(jì)</p><p>　　瓦倫蒂娜 斯道因那娃 庫肯斯卡</p>&l

92、t;p>　　摘要： 本文的內(nèi)容是用VHDL語言設(shè)計(jì)數(shù)字系統(tǒng)，按順序列出數(shù)字系統(tǒng)設(shè)計(jì)的所有步驟，此外，還有主要方法，介紹項(xiàng)目描述的類型，強(qiáng)調(diào) VHDL語言用于結(jié)構(gòu)的合成和行為模式。</p><p>　　對于創(chuàng)建項(xiàng)目所選擇的數(shù)字系統(tǒng)的集成系統(tǒng)使用了 WebPack，以及協(xié)同 XE II 的模型來進(jìn)行模擬的。</p><p>　　關(guān)鍵字： 設(shè)計(jì)，教程，數(shù)字系統(tǒng)、 WebPack 模型<

93、;/p><p><b>　　1.介紹</b></p><p>　　數(shù)字系統(tǒng)都是由復(fù)雜的大量組件組成的。對這種系統(tǒng)的自動化設(shè)計(jì)而言，應(yīng)該實(shí)現(xiàn)應(yīng)用方法設(shè)計(jì)時(shí)間的減少，以及限制任務(wù)的復(fù)雜性。這種方法應(yīng)遵循分解和層次結(jié)構(gòu)的原則，在職能上能區(qū)分獨(dú)立模塊的方式，實(shí)現(xiàn)系統(tǒng)的分解。</p><p>　　數(shù)字系統(tǒng)可以作為輸入和/或輸出模塊描述。對產(chǎn)出的電值是一些功能

94、上輸入的值。</p><p>　　描述一種模塊函數(shù)的一種方法是描述組成它的子模塊。每個(gè)子模塊是某些實(shí)體的實(shí)例和實(shí)例的端口使用信號進(jìn)行連接。這種描述方法被稱為結(jié)構(gòu)描述。</p><p>　　在許多情況下，是不適合用結(jié)構(gòu)描述的。其中一個(gè)元件是一個(gè)模塊，這是在其他一些結(jié)構(gòu)描述的層次結(jié)構(gòu)的底部的。例如，如果您正在用 從IC 商店購買的IC包設(shè)計(jì)一個(gè)系統(tǒng)，你不需要描述 IC 的內(nèi)部結(jié)構(gòu)。在這種情況下

95、，說明模塊執(zhí)行的功能是必需的，而不提及它實(shí)際的內(nèi)部結(jié)構(gòu)。這樣的描述被稱為功能或行為描述。</p><p>　　通常，結(jié)構(gòu)和行為的說明，需要Verilog 或者 VHDL語言。本文提供了超大規(guī)模集成電路的設(shè)計(jì)。在這里按順序列出了數(shù)字系統(tǒng)設(shè)計(jì)的所有階段，及其主要方法，介紹項(xiàng)目描述的類型，強(qiáng)調(diào) VHDL 用于合成結(jié)構(gòu)和行為模式。這里介紹幾種 VHDL 模型的計(jì)算機(jī)系統(tǒng)組件。</p><p>　　

96、2.數(shù)字系統(tǒng)設(shè)計(jì)的方法和階段</p><p>　　在數(shù)字系統(tǒng)設(shè)計(jì)，以及設(shè)計(jì)的復(fù)雜系統(tǒng)中，通常使用的幾個(gè)方法：</p><p>　　? ? 自頂向下設(shè)計(jì)</p><p>　　? ? 自底向上設(shè)計(jì)</p><p>　　自底向下的方法在通常從底部開始建立系統(tǒng)的設(shè)計(jì)方向，擬訂模塊的設(shè)計(jì)，通過組裝以后形成整個(gè)產(chǎn)品。</p><p&g

97、t;　　此方法的優(yōu)點(diǎn)是使用功能塊級別來實(shí)現(xiàn)，結(jié)構(gòu)級別較低，僅在項(xiàng)目中的錯誤檢查模擬過程中處理。</p><p>　　自頂向下設(shè)計(jì)始于最高水平的規(guī)范。之后，該項(xiàng)目被分解為功能塊，并且輸入輸出時(shí)間的比例可按需要指定。功能模型是通過行為模型或注冊級別的模型描述的，隨后進(jìn)行模擬。</p><p><b>　　此方法的優(yōu)點(diǎn)是：</b></p><p>　

98、　? ? 任務(wù)的規(guī)范更容易實(shí)現(xiàn)；</p><p>　　? ? 無需處理結(jié)構(gòu)的詳細(xì)信息，即可允許項(xiàng)目在制度層面上進(jìn)行檢查 ；</p><p>　　? ? 不用考慮到其實(shí)現(xiàn)的技術(shù)，項(xiàng)目的檢查就能完成。允許對設(shè)計(jì)項(xiàng)目的后期作出技術(shù)的選擇。</p><p>　　自頂向下設(shè)計(jì)的最有效方法是該計(jì)劃摘要說明的使用和指定順序詳細(xì)信息不同層次的描述。</p><

99、;p>　　數(shù)字系統(tǒng)設(shè)計(jì)經(jīng)歷的下一階段：</p><p><b>　　? ? 規(guī)范 ；</b></p><p>　　? ? 功能 （電子） 的設(shè)計(jì) ；</p><p>　　? ? 物理設(shè)計(jì) ；</p><p><b>　　? ? 制造 ；</b></p><p><

100、b>　　? ? 測試。</b></p><p>　　通過規(guī)范的產(chǎn)品參數(shù)，從而確定所需的正確目標(biāo)。</p><p>　　通過功能 （電子） 設(shè)計(jì)，電子設(shè)計(jì)，參照產(chǎn)品的規(guī)格來制定產(chǎn)品的函數(shù)和參數(shù)。</p><p>　　在行為階段中為系統(tǒng)方案而進(jìn)行的描述，其條目和出口已被標(biāo)出。在大多數(shù)情況下，使用 VHDL 模型。主要功能塊的完成需要功能 （電） 的設(shè)計(jì)

101、來處理。通常由 VHDL 功能塊的詳細(xì)說明來完成，以及通過VHDL 模擬進(jìn)行檢查。</p><p>　　隨著項(xiàng)目的日益復(fù)雜，在結(jié)構(gòu)層面上，需要應(yīng)用合成技術(shù)。它需要包含邏輯元素的方案通過VHDL語言描述來進(jìn)行綜合。通過邏輯描述的詳細(xì)信息如充電，元素的延誤，是被指定的關(guān)鍵的方法，并定義了時(shí)間離散信號的問題。</p><p>　　物理設(shè)計(jì)階段緊緊依賴于技術(shù)。邏輯元素的部署和它們之間聯(lián)系的定義 （

102、跟蹤） 與常見任務(wù)緊密相關(guān)。</p><p>　　在可編程邏輯器件的實(shí)現(xiàn)的條件下，可以使用 CPLD 或 FPGA 芯片，然后物理設(shè)計(jì)的結(jié)果則表示了設(shè)計(jì)所選設(shè)備的資源配置文件。</p><p>　　測試項(xiàng)目代表了設(shè)計(jì)師使用的一些程序，用于提供：</p><p>　　· 在項(xiàng)目和規(guī)范之間保持適中 ；</p><p>　　·

103、在所選擇的技術(shù)方面的項(xiàng)目執(zhí)行。</p><p>　　設(shè)計(jì)過程通常逐步實(shí)現(xiàn)，包括已獲得部分的預(yù)設(shè)計(jì)，直到獲得預(yù)期的指標(biāo)。</p><p>　　對于電氣設(shè)計(jì) （產(chǎn)品和其電氣參數(shù)的功能） 任務(wù)的測試，常用模擬來進(jìn)行。</p><p>　　在選擇其實(shí)際的混合模塊之前，行為層面上的模擬定義了產(chǎn)品將如何運(yùn)行。對于行為模式，應(yīng)使用硬件描述語言 (vhdl 語言、Verilog語言

104、和其他語言）。</p><p>　　通過模擬，在邏輯單元的級別上，由基本邏輯元素"與非"、"或非"、 轉(zhuǎn)換器和觸發(fā)器來建立系統(tǒng)，是為了找出與其預(yù)期行為的無關(guān)性。</p><p>　　在功能測試中，延遲是不相關(guān)，或者它們對于所有的邏輯元素來說類似。</p><p>　　物理設(shè)計(jì)后的錯誤鑒定</p><p>

105、;　　拓?fù)涞淖詈箨U述后進(jìn)行下一步程序：</p><p>　　? ? 在制作過程中檢查技術(shù)規(guī)范；</p><p>　　? ? 檢查項(xiàng)目的真實(shí)性。</p><p>　　針對每個(gè)工藝過程的制造技術(shù)規(guī)范都是被指定的。</p><p>　　項(xiàng)目真實(shí)性核查的目的是保證產(chǎn)品的正常工作。它包括：</p><p>　　? ? 找出互連的

106、方案 ；</p><p>　　? ? 找出拓?fù)涞募纳M件。</p><p><b>　　3.設(shè)計(jì)描述的類型</b></p><p>　　設(shè)計(jì)過程中，有三種類型的設(shè)計(jì)說明可以使用：</p><p><b>　　? ? 行為 ；</b></p><p><b>　　?

107、? 結(jié)構(gòu) ；</b></p><p><b>　　? ? 物理。</b></p><p>　　用行為描述處理系統(tǒng)，系統(tǒng)就像是一種只有入口和出口的"黑匣子"，而不顧其結(jié)構(gòu)。目的是忽略冗余的詳細(xì)信息，并致力于必要功能的詳細(xì)說明，以及所做產(chǎn)品的規(guī)范。在這一階段，使用 HDL （硬件描述語言）-vhdl 語言、Verilog 語言和其他語言。&

108、lt;/p><p>　　結(jié)構(gòu)的描述定義的方式為系統(tǒng)建立的方式。在這里，被處理的系統(tǒng)結(jié)構(gòu)是由塊和及其相互關(guān)系組成的。定義的子系統(tǒng)，是為提供其功能而執(zhí)行的，以及分析運(yùn)行速度，收費(fèi)等，以及其詳細(xì)說明。結(jié)構(gòu)描述可以用硬件描述語言來描述，如通過電子設(shè)計(jì)。</p><p>　　設(shè)計(jì)過程與系統(tǒng)描述和其順序詳細(xì)信息規(guī)范的轉(zhuǎn)換有緊密聯(lián)系。從行為描述到結(jié)構(gòu)描述進(jìn)行分解，可實(shí)現(xiàn)層次結(jié)構(gòu)中的某些級別。從最高到最低的這

109、些級別可以概述為，如下所示：</p><p>　　? ? 系統(tǒng)級別 ；</p><p>　　? ? 功能級別 ；</p><p>　　? ? 邏輯級別 ；</p><p><b>　　? ? 計(jì)劃級別。</b></p><p>　　系統(tǒng)的最高水平，描述其功能的算法由系統(tǒng)的行為所表示。這些函數(shù)被執(zhí)行