外文翻譯---基于dds參數(shù)可調(diào)諧波信號(hào)發(fā)生器的研究

1、<p><b>　　附錄A</b></p><p>　　Research of Parameter Adjustable Harmonic Signal Generator Based on DDS</p><p><b>　　LI Wei</b></p><p>　　College of Computer an

2、d Information Engineering Hohai University</p><p>　　Changzhou, 213022, China liwei_2142@163.com</p><p>　　ZHANG Jinbo</p><p>　　College of Computer and Information Engineering Hohai U

3、niversity Changzhou, 213022, China zhangjb@hhuc.edu.cn</p><p><b>　　Abstract</b></p><p>　　Harmonic signal generator whose frequency, phase and harmonic proportion are adjustable is de

4、signed for the detecting equipment of power system. The principle of DDS and the design requirement are introduced. Then the algorithm of ROM compression based on the symmetry of sine wave is expounded. Finally, using Al

5、tera FPGA, the detail design of the whole system is presented and test waveforms are given. Test results indicate that the system fulfils the design requirements.</p><p>　　1. Introduction</p><p>

6、;　　An ideal power system supplies power with sine wave, but the practical waveform of power supply often has many harmonic components. The basic reason of harmonic is that the power system supplies power to the electrica

7、l equipment with nonlinear characteristic. These nonlinear loads feed higher harmonic back to the power supply, and make the waveform of current and voltage in power system produce serious distortion. In the detection fi

8、eld of power system, standard signal generators which can simul</p><p>　　2. Principle of direct digital synthesis</p><p>　　Direct digital synthesis (DDS) is a new frequency synthesis technology

9、which directly synthesizes waveform on the basis of phase. Using the relationship between phase and amplitude, the phase of waveform is segmented and assigned relevant addresses. In each clock period, these addresses are

10、 extracted and the relevant amplitudes are sampled. The envelope of these sampled amplitudes is the expected waveform. If the clock frequency is constant, the frequency of output signal is adjustable with diff</p>

11、<p>　　DDS is composed of phase accumulator, ROM table, DAC and LPF. In each clock period, the output of phase accumulator is accumulated with frequency control word, and high L-bit of the output are used as address

12、 to query the ROM table. In the ROM, these addresses are converted to the sampled amplitudes of the expected waveform. Then DAC converts the sampled amplitudes to ladder wave. In the LPF, the ladder wave is smoothed, and

13、 the output is the continuous analog waveform.</p><p>　　Suppose that the clock frequency is fc, frequency control word is K, phase accumulator is N-bit, then output frequency is fout=(K/2N)fc, frequency reso

14、lution is Δfmin=fc/2N. According to the Nyquist Sample Criterion, output frequency upper limit is fmax<0.5fc. Because of the non-ideal characteristic of LPF, output frequency upper limit of DDS is fmax=0.4fc.</p>

15、;<p>　　3. Scheme design</p><p>　　3.1. Design requirements</p><p>　　The goal of the system is to design a harmonic signal generator, whose frequency, phase and harmonic proportion are adju

16、stable. The output waveform is composed of fundamental wave, 3th harmonic, 5th harmonic and 7th harmonic. Frequency resolution is 1Hz. The adjustable range of initial phase is 0~2π and its resolution is 1o. The adjustabl

17、e range of harmonic proportion is 0~50% and its resolution is 1%. According to the design requirements, system clock frequency is 15MHz and phase accumulator is</p><p>　　3.2. Algorithm of ROM compression<

18、/p><p>　　As is known, phase truncation error is the main factor of output waveform distortion. To avoid this, the ROM size must be exponentially increased, however the EAB of FPGA is limited. So the algorithm o

19、f ROM compression based on the symmetry of sine wave is adopted in the system. Sine wave of one period is divided into 4 sections: [0~π/2] 、[π/2~π] 、[π~3π/2] 、[3π/2~2π]. Using the symmetry of sine wave, sampled amplitude

20、s of the first section are stored in the ROM table. By address conversion and a</p><p>　　Sampled amplitudes of quarter wave are stored in the ROM table. The output address of phase accumulator is (L+2)-bit.

21、The low L-bit are used to query the ROM table while the high 2-bit are used to identify phase sections. When the highest bit is 1, the output of ROM table should be symmetrically converted by the amplitude convertor. Whe

22、n the second highest bit is 1, the L-bit address should be symmetrically converted by the address convertor.</p><p>　　4. System design based on FPGA</p><p>　　The system can be divided into two f

23、unction modules: sine wave generation module and harmonic synthesis module. Sine wave generation module is the key part of the system. It can be divided into phase accumulator module and ROM compression module . Altera F

24、PGA EP2C5Q208C8 is adopted as the core component of the system. VHDL is used to program the whole system. Compilation and simulation are implemented in Quartus Ⅱ.</p><p>　　4.1. Sine wave generation module<

25、;/p><p>　　phase accumulator module is composed of 24-bit accumulator and 11-bit adder. Under the control of system clock, the output of 24-bit accumulator is accumulated with 9-bit frequency control word. Then

26、11-bit adder adds 11-bit phase control word to the output of accumulator. High 13-bit of the final result are used as address to query the ROM compression module. ROM compression module is composed of address convertor,

27、amplitude convertor and ROM table. 13-bit address of phase accumulator module is</p><p>　　4.2. Harmonic synthesis module</p><p>　　Harmonic synthesis module implements the synthesis of fundamenta

28、l wave, 3th harmonic, 5th harmonic and 7th harmonic. The 3th, 5th and 7th harmonic data are respectively multiplied by their proportion control words. Then the results of multiplication are added to the fundamental wave

29、data. The realization of multiplication is the emphasis of the module. Because it is difficult to implement the multiplication of floating-point format on FPGA, harmonic proportion is divided into numerator and denom<

30、/p><p>　　5. Test results</p><p>　　Figure 7. Two-channel sine waves (frequency is</p><p>　　50Hz and phase difference is 180o)</p><p>　　Figure 8. Two-channel sine waves (fre

31、quency is</p><p>　　50Hz and phase difference is 120o)</p><p>　　Figure 9. Harmonic synthesis waveform</p><p>　　After the design of the system, the whole function is tested. Fig.7 sho

32、ws two-channel sine waves whose frequency is 50Hz and phase difference is 180o. Fig.8 shows two-channel sine waves whose frequency is 50Hz and phase difference is 120o. Fig.9 shows the harmonic synthesis waveform, whose

33、fundamental wave proportion is 100%, 3th harmonic proportion is 25%, and 5th harmonic proportion is 10%. Test waveforms indicate that the parameter adjustable harmonic signal generator fulfils the design requi</p>

34、<p>　　6. Conclusion</p><p>　　In the detection field of power system, standard signal generators which can simulate the power harmonic are highly needed to calibrate the power detecting equipment. To so

35、lve this problem, a harmonic signal generator whose frequency, phase and harmonic proportion are adjustable is presented. Using Altera FPGA, the whole system is implemented. Test results indicate that the adjustment and

36、stabilization precision of parameters meet the design requirements. This subject provides the exact basis fo</p><p>　　References</p><p>　　[1] Li Xiaoming and Qu xiujie, “Application of DDS/FPGA

37、in Signal Generator Systems”, Modern Electronics Technique, 2006：78-79.</p><p>　　[2] Yu Yong and Zheng Xiaolin, “Design and Implementation of Direct Digital Frequency Synthesis Sine Wave Generator Based on F

38、PGA”, Journal of Electron Devices, 2005：596-599.</p><p>　　[3] M.A. Taslakow, “Direct Digital Synthesizer with improved spectrum at low frequencies”, 2000 IEEE/EIA International Frequency Control Symposium an

39、d Exhibition, 2000：280-284.</p><p>　　[4] Yang Li and Li Zhen, “Multi-wave shape Signal Generator Based on FPGA”, Radio Engineering, 2005：46-48.</p><p>　　[5] D.J. Betowski and V. Beiu, “Considera

40、tions for phase accumulator design for Direct Digital Frequency Synthesizers”, IEEE International Conference on Neural Networks and Signal Processing, 2003：176-179.</p><p>　　[6] J. Vankka, “Methods of mappin

41、g from phase to sine in Direct Digital Synthesis”, 1996 IEEE International Frequency Control Symposium, 1996：942-950.</p><p>　　[7] K.A. Essenwanger and V.S. Reinhardt, “Sine output DDSs A survey of the state

42、 of the art”, 1998 IEEE International Frequency Control Symposium, 1998：370-376.</p><p><b>　　附錄B</b></p><p>　　基于DDS參數(shù)可調(diào)諧波信號(hào)發(fā)生器的研究</p><p><b>　　李煒</b></p>

43、;<p>　　學(xué)院計(jì)算機(jī)與信息工程河海大學(xué)</p><p>　　常州， 213022 ，中國(guó)liwei_2142@163.com</p><p><b>　　張金波</b></p><p>　　學(xué)院計(jì)算機(jī)與信息工程河海大學(xué)</p><p>　　常州， 213022 ，中國(guó)zhangjb@hhuc.edu.c

44、n</p><p><b>　　摘要</b></p><p>　　諧波信號(hào)發(fā)生器的頻率，相位和諧波比例可調(diào)的目的是為檢測(cè)設(shè)備的電源系統(tǒng)。介紹了DDS的原理和設(shè)計(jì)要求。然后在ROM的壓縮算法的基礎(chǔ)上闡述了正弦波的對(duì)稱性。最后，利用Altera的FPGA詳細(xì)的設(shè)計(jì)了整個(gè)系統(tǒng)，并給出了測(cè)試波形。實(shí)驗(yàn)結(jié)果表明，該系統(tǒng)滿足了設(shè)計(jì)要求。</p><p>&

45、lt;b>　　1簡(jiǎn)介</b></p><p>　　一個(gè)理想的電力系統(tǒng)是正弦波供電，但實(shí)際波形電源往往有許多諧波成分。產(chǎn)生諧波的基本原因是電力系統(tǒng)供電的電氣設(shè)備的非線性特性。這些非線性負(fù)載依靠高次諧波回到電源，使波形的電流和電壓的電力系統(tǒng)產(chǎn)生嚴(yán)重的失真。在電力系統(tǒng)的檢測(cè)領(lǐng)域，標(biāo)準(zhǔn)信號(hào)發(fā)生器可以模擬電力諧波非常需要標(biāo)定功率檢測(cè)設(shè)備，如相位檢測(cè)器，局部放電檢測(cè)儀，等等。因此，為參數(shù)可調(diào)諧波信號(hào)發(fā)生器的

46、研究提供準(zhǔn)確的依據(jù)和穩(wěn)定運(yùn)行的電力檢測(cè)設(shè)備，并具有很大的經(jīng)濟(jì)利益和社會(huì)價(jià)值。</p><p>　　2直接數(shù)字頻率合成的原理</p><p>　　直接數(shù)字合成（ DDS ）是一種在相位的基礎(chǔ)上直接合成波形的新的頻率合成技術(shù)，利用相位和振幅之間的關(guān)系，對(duì)相位的波形分割和分配有關(guān)的地址。在每一個(gè)時(shí)鐘周期，提取這些地址和有關(guān)振幅采樣。系統(tǒng)中這些被抽樣幅度是預(yù)期的波形。如果時(shí)鐘頻率是恒定的，頻率可調(diào)

47、輸出信號(hào)的地址可有不同提取步驟。</p><p>　　直接數(shù)字頻率合成器由累加器，存儲(chǔ)器， DAC和低通濾波器組成。在每一個(gè)時(shí)鐘周期，輸出相位累加器是由頻率控制字累計(jì)，高左旋位輸出作為地址查詢存儲(chǔ)器。在ROM中，這些地址被轉(zhuǎn)換為預(yù)期波形的抽樣振幅。然后數(shù)模轉(zhuǎn)換器轉(zhuǎn)換采樣振幅為階梯波。在低通濾波器，平滑階梯波，輸出的是連續(xù)的模擬波形。</p><p>　　假設(shè)時(shí)鐘頻率是fc，頻率控制字為K

48、，相位累加器為N位，則輸出頻率fout = （ K/2N ）fc，頻率分辨率是Δfmin = fc/2N 。根據(jù)奈奎斯特采樣標(biāo)準(zhǔn)，輸出頻率上限是fmax<0.5fc 。由于非理想特性的低通濾波器，DDS的輸出頻率上限的是fmax = 0.4fc。</p><p><b>　　3方案設(shè)計(jì)</b></p><p><b>　　3.1設(shè)計(jì)要求</b&g

49、t;</p><p>　　該系統(tǒng)的目標(biāo)是設(shè)計(jì)一個(gè)諧波信號(hào)發(fā)生器，其頻率相位和諧波比例可調(diào)。輸出波形是由基波，第三諧波，第五次諧波和第七次諧波構(gòu)成。頻率分辨率是1赫茲。可調(diào)范圍的初始階段為0~2π，其圖形分辨率為1?？烧{(diào)范圍的諧波比例為0~50％，其圖形分辨率是1％。根據(jù)設(shè)計(jì)要求，系統(tǒng)時(shí)鐘頻率是15MHz，相位累加器是24位。為了產(chǎn)生最多的EAB,采用211×8位ROM。11位相位控制字是用來滿足初始階段

50、的圖形分辨率。7位比例控制字采用正確設(shè)定的諧波比例。</p><p><b>　　3.2ROM的算法</b></p><p>　　正如人們所知，相位截?cái)嗾`差的主要因素是輸出波形畸變。為避免出現(xiàn)這種情況，ROM大小必須成倍增加，但EAB的FPGA是有限的。因此，該算法壓縮的ROM基于系統(tǒng)中正弦波的對(duì)稱性。正弦波一期分為4個(gè)部分：[0~π/2]，[π/2~ π]，[π~3

51、π/2]，[3π/2~2π]。使用對(duì)稱的正弦波，取樣振幅的第一部分都存儲(chǔ)在ROM。通過地址轉(zhuǎn)換和振幅轉(zhuǎn)換，一期正弦波的采樣振幅可以生成。通過這一手段，ROM大小是之前大小的四分之一。在相同的ROM中應(yīng)用這種方法，采樣點(diǎn)可提高4倍。</p><p>　　采樣波振幅分塊存儲(chǔ)在ROM中。輸出相位累加器地址是（L+2）-bit。低左旋位是用來查詢表的ROM，而高2位是用來識(shí)別階段部分。當(dāng)最高位為1 ，輸出的ROM表為對(duì)稱

52、轉(zhuǎn)換的幅度變換器。當(dāng)?shù)诙€(gè)最高位是1 ，L型位地址為對(duì)稱轉(zhuǎn)換的地址轉(zhuǎn)換。</p><p>　　4基于FPGA的系統(tǒng)設(shè)計(jì)</p><p>　　該系統(tǒng)可分為兩個(gè)功能模塊：正弦波代模塊和諧波合成模塊。正弦波代模塊是系統(tǒng)中關(guān)鍵的部分。它可分為階段累加器模塊和ROM壓縮模塊。Altera的FPGA EP2C5Q208C8是該系統(tǒng)的核心組成部分，VHDL語言用來設(shè)計(jì)整個(gè)系統(tǒng)。匯編和仿真使用Quartu

53、s Ⅱ 實(shí)現(xiàn)。</p><p>　　4.1正弦波生成模塊</p><p>　　相位累加器模塊由24位累加器和11位加法器組成的。系統(tǒng)時(shí)鐘所控制的是9位頻率控制字與24位累加器的相加的輸出。然后11位相位控制字增加了11位加法器和累加器的輸出。高13位的最后結(jié)果被用作處理查詢正弦數(shù)據(jù)查詢ROM模塊。正弦數(shù)據(jù)查詢ROM模塊是由地址轉(zhuǎn)換，振幅轉(zhuǎn)換器和ROM模塊組成的。13位地址相位累加器模塊分為

54、三部分。最高位被用作觸發(fā)信號(hào)的幅度變換器。第二個(gè)最高位被用作觸發(fā)信號(hào)的地址轉(zhuǎn)換。低11位是用來查詢正弦數(shù)據(jù)查詢ROM模塊。然后取樣振幅產(chǎn)生正弦波。正弦波信號(hào)發(fā)生器模塊的仿真結(jié)果正確。頻率控制字設(shè)置為50，而相位控制字設(shè)置為180。當(dāng)時(shí)鐘控制信號(hào)變成低電平時(shí)，第一個(gè)產(chǎn)生數(shù)值是ROM模塊中地址為180時(shí)所對(duì)應(yīng)的正弦波的值。系統(tǒng)時(shí)鐘的每個(gè)上升沿產(chǎn)生波形數(shù)據(jù)地址所對(duì)應(yīng)的180，181，182，183。其產(chǎn)生的數(shù)值分別為76，76，77，77。&

55、lt;/p><p><b>　　4.2諧波合成模塊</b></p><p>　　諧波合成模塊完成的是基波，第三次諧波，第五次諧波和第七次諧波的合成。第三次，第五次和第七次諧波數(shù)據(jù)分別乘以其比例控制字。然后其相乘的結(jié)果再加上基波數(shù)據(jù)。其結(jié)果實(shí)現(xiàn)的是增強(qiáng)電路模塊。因?yàn)榛贔PGA很難實(shí)施多元化的浮點(diǎn)格式，調(diào)和比例的劃分結(jié)果分為分子和分母。分子被定義為比例控制字而分母為100。

56、首先,諧波的數(shù)據(jù)是乘以這個(gè)比例控制字的乘數(shù)。然后，這個(gè)相乘后的結(jié)果再在觸發(fā)其里除以100。最后，剩下的是余數(shù)和商被保存了下來。使用Altera IP工具、乘法器和除法來實(shí)現(xiàn)器諧波合成模塊。框圖的諧波合成將被顯示。諧波合成模塊的仿真結(jié)果正確。使用2.0ms以內(nèi)的控制字的話?；ǖ念l率為50赫茲，其初始相位是0度。第三次諧波頻率為150赫茲，其初始相位是45度和比例為50%。第五次諧波頻率是250赫茲, 其初始相位是90度和比例是25%。第

57、七次諧波頻率是350Hz, 其初始相位是135度和比例是17%。當(dāng)時(shí)鐘控制信號(hào)轉(zhuǎn)變成低電平時(shí)，諧波合成模塊開始產(chǎn)生所合成的諧波的數(shù)據(jù)。</p><p><b>　　5測(cè)試結(jié)果</b></p><p>　　經(jīng)過系統(tǒng)的設(shè)計(jì)，整體功能的測(cè)試。圖7顯示雙通道正弦波，其頻率為50赫茲和相位差是180度。圖8顯示雙通道正弦波，其頻率為50赫茲和相位差是120度。圖9顯示了諧波合成

58、波形，其基波比例為100％，第三諧波的比例是25％，和第5次諧波的比例是10％。試驗(yàn)表明，波形參數(shù)可調(diào)諧波信號(hào)發(fā)生器滿足了設(shè)計(jì)要求。</p><p>　　圖 7 雙通道正弦波（頻率</p><p>　　50，相位差是180o ）</p><p>　　圖 8 雙通道正弦波（頻率</p><p>　　50，相位差是120o ）</p>

59、<p><b>　　圖9 諧波合成波形</b></p><p><b>　　6結(jié)論</b></p><p>　　在電力系統(tǒng)的檢測(cè)領(lǐng)域，標(biāo)準(zhǔn)信號(hào)發(fā)生器模擬電力諧波非常精確的標(biāo)定功率檢測(cè)設(shè)備。為了解決這個(gè)問題，介紹了一種頻率，相位和諧波比例可調(diào)的諧波信號(hào)發(fā)生器。利用Altera的FPGA實(shí)現(xiàn)了整個(gè)系統(tǒng)的實(shí)施。試驗(yàn)結(jié)果表明，調(diào)整和穩(wěn)定精度

60、的參數(shù)達(dá)到設(shè)計(jì)要求。這一主題提供了準(zhǔn)確的依據(jù)，穩(wěn)定運(yùn)行的電力檢測(cè)設(shè)備，具有強(qiáng)大的經(jīng)濟(jì)利益和社會(huì)價(jià)值。</p><p><b>　　參考文獻(xiàn)</b></p><p>　　[ 1 ]李曉明，曲秀杰，“DDS/FPGA在信號(hào)發(fā)生器的系統(tǒng)的應(yīng)用”，現(xiàn)代電子技術(shù)，2006年：78-79</p><p>　　[ 2 ]于育，鄭小琳，“基于FPGA的直接數(shù)字

61、頻率合成正弦波發(fā)生器的設(shè)計(jì)與實(shí)現(xiàn)”，電子器件雜志，2005年：596-599</p><p>　　[ 3 ]M.A. Taslakow，“改進(jìn)頻譜低頻的直接數(shù)字頻率合成器”，2000年的IEEE /頻率控制的環(huán)境影響評(píng)估國(guó)際研討會(huì)及展覽， 2000年：280-284</p><p>　　[ 4 ]楊力，李鎮(zhèn)，“多波形信號(hào)發(fā)生器的FPGA實(shí)現(xiàn)”，無線電工程系， 2005年：46-48<

62、/p><p>　　[ 5 ] D.J. Betowski， V. Beiu，“思考階段累加器設(shè)計(jì)直接數(shù)字頻率合成器”，IEEE國(guó)際會(huì)議的神經(jīng)網(wǎng)絡(luò)和信號(hào)處理，2003年：176-179</p><p>　　[ 6 ] J. Vankka，“以正弦波直接數(shù)字頻率合成方法測(cè)繪階段”，1996年IEEE國(guó)際頻率控制專題討論會(huì)，1996年：942-950</p><p>　　[