應用于usb2.0時鐘數(shù)據(jù)恢復的鎖相環(huán)設計

1、上海交通大學碩士學位論文應用于USB2.0時鐘數(shù)據(jù)恢復的鎖相環(huán)設計姓名：潘瑞雪申請學位級別：碩士專業(yè)：軟件工程（集成電路設計）指導教師：周健軍20080101上海交通大學專業(yè)學位碩士學位論文 - II - Design of phase-locked loop for usb2.0 application Abstract Abstract In the digital communication and high speed tra

2、nsceiver field, clock and data recovery circuit is widely used. Providing a low jitter, process independent clock to the receiver is a very important part. This study is trying to design a completely monolithic phase-loc

3、ked loop (PLL), which is used for usb2.0 clock generation and NRZ data recovery application. The design work is from top level design to all the bottom blocks, including Phase detector, Charge Pump, Low pass filter, VCO

4、and other auxiliary circuits by TSMC 0.18um CMOS process and 3.3V power supply. The paper describes the PLL system theory, cell circuit design and simulation, and loop simulation. All the simulation results satisfy high