外文翻譯--在一個(gè)快速邏輯fpga中的調(diào)制直接數(shù)字頻率合成器

1、英文資料及中文翻譯Modulating Direct Digital Synthesizer in a QuickLogic FPGADDS Overview:In the pursuit of more complex phase continuous modulation techniques, the control of the output waveform becomes increasingly more difficul

2、t with analog circuitry. In these designs, using a non-linear digital design eliminates the need for circuit board adjustments over yield and temperature. A digital design that meets these goals is a Direct Digital Synth

3、esizer DDS. A DDS system simply takes a constant reference clock input and divides it down a to a specified output frequency digitally quantized or sampled at the reference clock frequency. This form of frequency control

4、 makes DDS systems ideal for systems that require precise frequency sweeps such as radar chirps or fast frequency hoppers. With control of the frequency output derived from the digital input word, DDS systems can be used

5、 as a PLL allowing precise frequency changes phase continuously. As will be shown, DDS systems can also be designed to control the phase of the output carrier using a digital phase word input. With digital control over t

6、he carrier phase, a high spectral density phase modulated carrier can easily be generated. This article is intended to give the reader a basic understanding of a DDS design, and an understanding of the spurious output re

7、sponse. This article will also present a sample design running at 45MHz in a high speed field programmable gate array from QuickLogic.A basic DDS system consists of a numerically controlled oscillator (NCO) used to gener

8、ate the output carrier wave, and a digital to analog converter (DAC) used to take the digital sinusoidal word from the NCO and generate a sampled analog carrier. Since the DAC output is sampled at the reference clock fre

9、quency, a wave form smoothing low pass filter is typically used to eliminate alias components. Figure 1 is a basic block diagram of a typical DDS system design.The generation of the output carrier from the reference samp

10、le clock input is performed by the NCO. The basic components of the NCO are a phase accumulator and a sinusoidal ROM lookup table. An optional phase modulator can also be include in the NCO design. This phase modulator w

11、ill add phase offset to the output of the phase accumulator just before the ROM lookup table. This will enhance the DDS system design by adding the capabilities to phase modulate the carrier output of the NCO. Figure 2 i

12、s a detailed block diagram of a typical NCO design showing the optional phase modulator. FIGURE 1: Typical DDS System. FIGURE 2: Typical NCO Design. 2feature is not demonstrated in the sample QuickLogic FPGA design. Fina

13、lly, frequency modulation is a given with the basic NCO design. The frequency port can directly adjust the carrier output frequency. Since frequency words are loaded into the DDS synchronous to the sample clock, frequenc

14、y changes are phase continuous. Although DDS systems give the designer complete control of complex modulation synthesis, the representation of sinusoidal phase and magnitude in a non-linear digital format introduces new

15、design complexities. In sampling any continuous-time signal, one must consider the sampling theory and quantization error. To understand the effects of the sampling theory on a DDS system, it is best to look at the DDS s

16、ynthesis processes in both the time and frequency domain. As stated above, the NCO generates a sinusoidal wave form by accumulating the phase at a specified rate and then uses the phase value to address a ROM table of si

17、nusoidal amplitude values. Thus, the NCO is essentially taking a sinusoidal wave form and sampling it with the rising or falling edge of the NCO input reference sampling clock. Figure 4 shows the time and frequency domai

18、n of the NCO processing. Note that this representation does not assume quantization. Based on the loaded frequency word, the NCO produces a set of amplitude output values at a set period. The frequency domain representat

19、ion of this sinusoid is an impulse function at the specified frequency. The NCO, however, outputs discrete digital samples of this sinusoid at the NCO reference clock rate. In the time domain, the NCO output is a functio

20、n of the sampling clock edge strobes multiplied by the sinusoid wave form producing a train of impulses at the sinusoid amplitude. In the frequency domain, the sampling strobes of the reference clock produce a train of i

21、mpulses at frequencies of K times the NCO clock frequency where K = ... - 1, 0, 1, 2 .... Since the sampling clock was multiplied by the sinusoid in the time domain, the frequency domain components of the sinusoid and th

22、e sampling clock need to be convolved to produce the frequency domain representation of the NCO output. The frequency domain results are the impulse function at the fundamental frequency of the sinusoid and the alias imp

23、ulse functions occurring at K times the NCO clock frequency plus or minus the fundamental frequency. The fundamental and alias component occur at: K*Fclk - Fout K*Fclk + Fout Where K = ... -1, 0 , 1, 2 ..... and K = 0 is