外文翻譯---數(shù)字頻率合成器

1、<p><b>　　附錄3：英文原文</b></p><p>　　Modulating Direct Digital Synthesizer </p><p>　　In the pursuit of more complex phase continuous modulation techniques, the control of the output w

2、aveform becomes increasingly more difficult with analog circuitry. In these designs, using a non-linear digital design eliminates the need for circuit board adjustments over yield and temperature. A digital design that m

3、eets these goals is a Direct Digital Synthesizer DDS. A DDS system simply takes a constant reference clock input and divides it down a to a specified output frequency digitally quant</p><p>　　This article is

4、 intended to give the reader a basic understanding of a DDS design, and an understanding of the spurious output response. This article will also present a sample design running at 45MHz in a high speed field programmable

5、 gate array from QuickLogic.</p><p>　　A basic DDS system consists of a numerically controlled oscillator (NCO) used to generate the output carrier wave, and a digital to analog converter (DAC) used to take t

6、he digital sinusoidal word from the NCO and generate a sampled analog carrier. Since the DAC output is sampled at the reference clock frequency, a wave form smoothing low pass filter is typically used to eliminate alias

7、components. Figure 1 is a basic block diagram of a typical DDS system design.The generation of the output carri</p><p>　　FIGURE 1: Typical DDS System. </p><p>　　FIGURE 2: Typical NCO Design. <

8、;/p><p>　　To better understand the functions of the NCO design, first consider the basic NCO design which includes only a phase accumulator and a sinusoidal ROM lookup table. The function of these two blocks of

9、 the NCO design are best understood when compared to the graphical representation of Euler’s formula ej wt = cos( wt) + jsin( wt). The graphical representation of Euler’s formula, as shown in Figure 3, is a unit vector r

10、otating around the center axis of the real and imaginary plane at a velocity of </p><p>　　This frequency word is continuously accumulated with the last sampled phase value by an N bit adder. The output of th

11、e adder is sampled at the reference sample clock by an N bit register. When the accumulator reaches the N bit maximum value, the accumulator rolls over and continues. Plotting the sampled accumulator values versus time p

12、roduces a saw tooth wave form as shown below in Figure 3. </p><p>　　FIGURE 3 Euler’s Equation Represented Graphically</p><p>　　The sampled output of the phase accumulator is then used to address

13、 a ROM lookup table of sinusoidal magnitude values. This conversion of the sampled phase to a sinusoidal magnitude is analogous to the projection of the real or imaginary component in time. Since the number of bits used

14、by the phase accumulator determines the granularity of the frequency adjustment steps, a typical phase accumulator size is 24 to 32 bits. Since the size of the sinusoidal ROM table is directly proportional to the </p&

15、gt;<p>　　Since an NCO outputs a carrier based on a digital representation of the phase and magnitude of the sinusoidal wave form, designers have complete control over frequency, phase, and even amplitude of the ou

16、tput carrier. By adding a phase port and a phase adder to the basic NCO design, the output carrier of the NCO can be M array phase modulated where M equals the number of phase port bits and where M is less than or equal

17、to the Y number of bits used to address the sinusoidal ROM table. For system</p><p>　　Although DDS systems give the designer complete control of complex modulation synthesis, the representation of sinusoidal

18、 phase and magnitude in a non-linear digital format introduces new design complexities. In sampling any continuous-time signal, one must consider the sampling theory and quantization error. </p><p>　　To unde

19、rstand the effects of the sampling theory on a DDS system, it is best to look at the DDS synthesis processes in both the time and frequency domain. As stated above, the NCO generates a sinusoidal wave form by accumulatin

20、g the phase at a specified rate and then uses the phase value to address a ROM table of sinusoidal amplitude values. Thus, the NCO is essentially taking a sinusoidal wave form and sampling it with the rising or falling e

21、dge of the NCO input reference sampling clock. Figure</p><p>　　Based on the loaded frequency word, the NCO produces a set of amplitude output values at a set period. The frequency domain representation of th

22、is sinusoid is an impulse function at the specified frequency. The NCO, however, outputs discrete digital samples of this sinusoid at the NCO reference clock rate. In the time domain, the NCO output is a function of the

23、sampling clock edge strobes multiplied by the sinusoid wave form producing a train of impulses at the sinusoid amplitude. In the frequen</p><p>　　The frequency domain results are the impulse function at the

24、fundamental frequency of the sinusoid and the alias impulse functions occurring at K times the NCO clock frequency plus or minus the fundamental frequency. The fundamental and alias component occur at: </p><p&

25、gt;　　K*Fclk - Fout </p><p>　　K*Fclk + Fout </p><p>　　Where K = ... -1, 0 , 1, 2 ..... and K = 0 is the NCO sinusoid fundamental frequency </p><p>　　Fout is the specified NCO sinusoi

26、d output frequency </p><p>　　Fclk is the NCO reference clock frequency </p><p>　　FIGURE 4 NCO Output Representation Time and Frequency Domain</p><p>　　The DAC of the DDS system take

27、s the NCO output values and translates these values into analog voltages. Figure 4 shows the time and frequency domain representations of the DAC processing starting with the NCO output. The DAC output is a sample and ho

28、ld circuit that takes the NCO digital amplitude words and converts the value into an analog voltage and holds the value for one sample clock period. The time domain plot of the DAC processing is the convolution of the NC

29、O sampled output values with a</p><p>　　Atten(F) = 20log[(sin(pF/Fclk)/pF/Fclk)] Where F is the output frequency Fclk is the sample clock frequency </p><p>　　FIGURE 5: DAC Output Representation

30、in Time and Frequency Domain </p><p>　　Aside from the sampling theory, the quantization of the real values into digital form must also be considered in the performance analysis of a DDS system. The spurious

31、response of a DDS system is primarily dictated by two quantization parameters. These parameters are the phase quantization by the phase accumulator and the magnitude quantization by the ROM sinusoidal table and the DAC.

32、</p><p>　　As mentioned above, only the upper Y bits of the phase accumulator are used to address the ROM lookup table. It should be noted, however, that using only the upper Y bits of the phase accumulator i

33、ntroduces a phase truncation. When a frequency word containing a non-zero value in the lower (N-Y-1:0) bits is loaded into the DDS system, the lower non-zero bits will accumulate to the upper Y bits and cause a phase tru

34、ncation. The frequency at which the phase truncation occurs can be calculated by th</p><p>　　Ftrunc = FW(N-Y- 1:0)/2N-Y* Fclk. </p><p>　　A phase truncation will periodically (at the Ftrunc rate)

35、 phase modulate the output carrier forward 2p/28 to compensate for frequency word granularity greater than 2Y. The phase jump caused by the accumulation of phase truncated bits produces spurs around the fundamental.</

36、p><p>　　These spurs are located plus and minus the truncation frequency from the fundamental frequency and the magnitude of the spurs will be - 20log(2Y)dBc. A sample output of a phase truncation spur is shown

37、in Figure 5. </p><p>　　In a typical NCO design, the ROM sinusoidal table will hold a ¼ sine wave (0 , p/2) of magnitude values. The ROM table is generated by taking all possible phase value addresses an

38、d map to a real magnitude sine value rounded to the nearest D bits. Thus, the maximum error output is ±- ½ LSB giving a worst case spur of -20log(2D)dBc. </p><p>　　Like the NCO ROM table, a DAC qua

39、ntizes the digital magnitude values. A DAC, however, outputs an analog voltage corresponding to the digital input value. When designing the NCO sinusoidal ROM table, one should take some empirical data on the DAC lineari

40、ty to better understand the interaction between the ROM table and the DAC. The quantization for a DAC is specified against an ideal linear plot of digital input versus analog output. Two linearity parameters, differentia

41、l and integral linearity, a</p><p>　　Differential linearity is the output step size from bit to bit. A DAC must guarantee a differential linearity of a maximum 1 LSB. When an input code is increased, the DAC

42、 output must increase. If the DAC voltage does not increase versus an increase digital input value, the DAC is said to be missing codes. Thus, a 10 bit DAC that has a differential linearity of greater that 1 LSB is only

43、accurate to 9 or less bits. The number of accurate output bits will specify the DDS spurious performance as -2</p><p>　　Integral linearity is a measure of the DAC’s overall linear performance versus an ideal

44、 linear straight line. The straight line plot can be either a “best straight line” where DC offsets are possible at both the min and max outputs of the DAC, or the straight line can cross the end points of the min and ma

45、x output values. A DAC will tend to have a characteristic curve that is traversed over the output range. Depending on the shape and symmetry (symmetry about the half way point of the DAC output</p><p>　　Othe

46、r DAC characteristic that will produce harmonic distortion is any disruption of the symmetry of the output wave form such as a different rise and fall time. These characteristics can typically be corrected by board compo

47、nents external to the DAC such as an RF transformer, board layout issues, attenuation pads etc. </p><p>　　Given the complexities of the DDS system, engineers should consider implementing the design using sep

48、arate devices for the numerically controlled oscillator, the digital to analog converter, and the low pass filter. This approach allows for signal observation at many points in the system, yet is compact enough to be pra

49、ctical as an end-solution. Alternatively, the discrete implementation can serve as a prototyping vehicle for a single-chip mixed signal ASIC. </p><p>　　The author developed a version of the design using a Ha

50、rris HI5721 evaluation board for the DAC. The NCO at the heart of the DDS design, and a random generator to test signal modulation, was implemented into about 65% of a QuickLogic field programmable gate array (FPGA). Thi

51、s FPGA, a QL16x24B 4000-gate device, was chosen for its high performance, ease-of-use, and powerful development tools. </p><p>　　The NCO design included following:</p><p>　　Developed in Verilog

52、with the 8 bit CLA adder schematic </p><p>　　captured and net listed to Verilog</p><p>　　32 bit frequency word input </p><p>　　32 phase accumulator pipelined over 8 bits</p>

53、<p>　　8 bit phase moudulation word input</p><p>　　8 bit sine ROM look-up table</p><p>　　The design was described mostly in Verilog, with an 8 bit carry look ahead adder modified from QuickL

54、ogic’s macro library netlisted to Verilog. The whole design cycle was less than four days (two days to describe the design and a day and a half to prototype the hardware). Everything worked perfectly the first time, with

55、 the design running at an impressive 45MHz as predicted by the software simulation tools. </p><p>　　Plots used in the article to illustrate DDS performance parameters were provided from the test configuratio

56、n. </p><p>　　Figure 6 below shows the external IO interface to the NCO design .The function of each signal is described in the following table.</p><p>　　Signal Function Table </p><p&g

57、t;　　Figure 6: The External IO Interface </p><p>　　Top Level (dds.v) </p><p>　　The top level of the NCO design instantiates the functional blocks of the NCO design and the PN generator block. <

58、;/p><p>　　PN Generator (pngen.v) </p><p>　　This module is not part of the NCO design but is used to produce a sample random data pattern to modulate the carrier output. This module uses the PNCLK i

59、nput to clock two Gold code 5 bit PN generators. The outputs of the PN generators are IDATA and QDATA outputs. </p><p>　　The lower level block of this NCO design consist of a synchronous frequency word input

60、 register, a synchronous phase word input register, a 32 bit pipe lined phase accumulator, an 8 bit phase adder, and a sin lockup table. A detailed description of each of the NCO blocks and the PN generator are provided

61、in the following sections. </p><p>　　Load Frequency Word (loadfw.v) </p><p>　　The load frequency word block is a synchronizing loading circuit. The FREQWORD[31:0] input drives a the data input t

62、o the 32 bit fwreg register that is sampled on the rising edge of the FWWRN write strobe. The FWWRN strobe also drives the data input to a metastable flip flop fwwrnm that is used in conjunction with a synchronous regist

63、er fwwrns to produce a FWWRN rising edge strobe. This rising edge strobe loadp1 is then piped for an additional 3 clock cycles producing the load strobes loadp2, lo</p><p>　　Phase Word Accumulator (phasea.v)

64、 </p><p>　　The phase accumulator block is a 32 bit accumulator that is pipe lined in 8 bit sections. This module instanciates a schematic captured carry lock ahead CLA adder that has a carry in and carry out

65、 port. The synchronous frequency word, staggered to match the pipe lined accumulator, is loaded into the B input of the CLA adders. The sum output of the CLA adders are registered in the pipe registered with the output t

66、ied back to the A input of the CLA adders. The carry output of the CLA adders is reg</p><p>　　Load Phase Word (loadpw.v) </p><p>　　The load phase word block is a synchronizing loading circuit. T

67、he PHASEWORD[7:0] input drives the data input to the 32 bit pwreg register that is sampled on the rising edge of the PWWRN write strobe. The PWWRN strobe also drives the data input to a metastable flip flop pwwrnm that i

68、s used in conjunction with a synchronous register pwwrns to produce a FWWRN rising edge strobe. This rising edge strobe load is used to signal when to update the synchronous phase word register phswd. The phswd regist<

69、;/p><p>　　Phase Modulator (phasemod.v) </p><p>　　The phase modulator block is used to phase offset the phase accumulator 8 bit quantized output with the synchronous phase word from the load phase w

70、ord block. This module instantiates a CLA adder with the A input tied to the synchronous phase output and the B input tied to the phase accumulator output. The sum output of the adder is registered in the mphsreg registe

71、r and assigned to the MODPHASE output port. A modulated version of the sine and cosine values are calculated and brought out of the </p><p>　　Sine Lockup (sinlup.v) </p><p>　　This module takes t

72、he modulated phase value form the phase modulator block and translated the quantized 8 bit value into a sine wave form amplitude value quantized to 8 bits. The translation from phase to amplitude is performed by a sine R

73、OM table that in instantiated in this module. The ROM table is reduced to a ¼ of the symmetrical sine wave form and the MSB of the sine wave form is equivalent to the modulated phase input.This module performs the c

74、alculations to reconstruct a complete period o</p><p>　　This module manages the address values to the ROM table and the amplitude outputs to form the complete period of the sine wave form. The first process

75、of generating the sine wave function is the addressing of the ROM table such that phase angles p/2 to p and 3p/2 to 2p are addressed in the reverse order. Reverse addressing is accomplished by simply inverting the ROM ta

76、ble address input vector. The phase modulated address input is inverted when the MODPHASE[6] is one and is then registered in the</p><p>　　Sine ROM Table (romtab.v) </p><p>　　This module is the

77、sine wave form ROM table. This table converts the phase word input to a sine amplitude output. To conserve area, only ¼ of the symmetrical sine wave form is stored in the ROM. The sine values stored in this table ar

78、e the 0 to p/2 unsigned values quantized to 8 bits. Thus, the ROM table requires a 6 bit phase address input and outputs a 7 bit amplitude output. The sinlup module processes the phase and amplitude values to produce a

79、complete sine period. </p><p>　　Dan Morelli has over 9 years of design and management experience. His areas of expertise include spread spectrum communications (involving GPS, TDRSS, and 802.11), PC chip set

80、 and system architecture, cell library development (for ECL devices) and ASIC development. He has been published and has multiple patents awarded and pending. Dan currently works for Accelent Systems Inc., an electronic

81、design consulting company, where he is a founder and the VP of Engineering.</p><p><b>　　附錄4：中文譯文</b></p><p><b>　　數(shù)字頻率合成器</b></p><p>　　在探討許多復雜的相位連續(xù)的調制技術中，對模擬電

82、路中輸出波形的控制已經(jīng)越來越困難。在這些設計中，使用非線性數(shù)字式設計除去電路板需要的調整額外輸出和溫度。一個適合這個目標的數(shù)字式設計就是直接數(shù)字頻率合成器（DDS）。一個DDS系統(tǒng)僅僅使用一個恒定參考時鐘輸入和將該時鐘分解為指定的量化數(shù)位頻率輸出或者對參考時鐘頻率取樣。這種形式是頻率控制使得DDS系統(tǒng)成為需要精確頻率掃描比如雷達尖叫聲或者快速頻率計量器的理想系統(tǒng)。根據(jù)數(shù)字輸入控制字以控制輸出頻率，DDS系統(tǒng)可以用來當作一個允許精確頻率連

83、續(xù)改變相位的鎖相環(huán)（PLL）。根據(jù)后面的說明，我們知道DDS系統(tǒng)還可以使用輸入數(shù)字相位控制字來控制輸出載波的相位。用數(shù)字式控制載波相位，很容易產(chǎn)生一個高頻譜密度的相位調制載波。</p><p>　　本文主旨是給讀者一個基本的DDS設計和寄生輸出響應的知識。本文將展示一個運行于45MHz的快速現(xiàn)場可編輯邏輯器件。</p><p>　　一個基本的DDS系統(tǒng)包括一個數(shù)字振蕩器（NCO）用來產(chǎn)生輸

84、出載波，和一個數(shù)模轉換器（DAC）用來將從NCO過來的數(shù)字式正弦曲線字產(chǎn)生一個抽樣的模擬載波。當DAC的輸出是根據(jù)參考時鐘頻率的抽樣時，通常用一個圓滑波形的低通濾波器來消除混疊成分。根據(jù)輸入的參考時鐘抽樣經(jīng)過NCO來產(chǎn)生輸出載波。NCO的基本構成是一個相位累加器和一個正弦ROM查找表。通過增加NCO的載波相位調制的輸出能力可以提高DDS系統(tǒng)的設計。</p><p>　　為了更好的理解NCO設計的各種功能，首先考慮

85、僅包括一個相位累加器和一個正弦ROM查找表的基本NCO設計。與歐拉公式（Euler’s formula）圖解比較就能最好地理解這兩個表的NCO設計的功能。歐拉公式的圖解如圖3所示，是一個單位向量繞著實軸和虛平面的中心以W rad/s的速度轉圈。</p><p>　　這個頻率控制字是最后一個抽樣相位值通過一個N位加法器的連續(xù)地累加而成。加法器的輸出是參考抽樣時鐘通過一個N位寄存器的抽樣。當累加器達到N位最大值的時候

86、，累加器翻轉然后繼續(xù)。然后相位累加器的抽樣輸出用來在一個正弦量化值表里進行查找。抽樣相位到正弦量化的轉化可以看作是真實的或者虛擬的成分及時地影射。因為相位累加器的比特位數(shù)決定了頻率調整的步進，一個典型的相位累加器的大小是24到32位。由于正弦ROM表的大小是跟尋址范圍直接成比例的，因此，不是所有相位累加器的24或32位都用來作為正弦ROM表的地址。僅是相位累加器的高Y（Y〈N〉位是用來作為正弦ROM表的地址，Y通常不必要等于正弦ROM表

87、的輸出量位D。</p><p>　　因為一個NCO輸出的一個基于一個數(shù)字表示的相位和正弦波量化形式的載波，所以設計者可以完全的控制輸出載波的頻率，相位和幅度。通過加入一個相位端口和一個相位加法器到一個基本的NCO設計中，NCO的輸出載波當M等于相位端口數(shù)和M小于或等于Y（用來作為正弦ROM表的地址位數(shù)）時可以被M矩陣相位調制。假如系統(tǒng)設計需要幅度調制如QAM，可以加入一個量化端口來調整正弦ROM表的輸出。注意到這

88、個端口沒有在圖2里表示出來以及這個特色沒有在簡單的快速邏輯FPGA設計中論證。最后，頻率是調制是一個基本的NCO設計給出的。因為頻率控制字是跟抽樣時鐘是同步裝載到DDS的，頻率的轉化是相位連續(xù)的。</p><p>　　雖然DDS系統(tǒng)給設計者完全地控制復雜的調制合成，但是在一個非線性數(shù)字格式的正弦相位和量級的表示卻是復雜的新設計。在取樣任何的連續(xù)時間信號時，必須考慮取樣原理和量子化誤差。</p>&l

89、t;p>　　為了理解DDS系統(tǒng)中取樣理論的效果，最好看一下時間和頻率域的DDS合成過程。就象上面規(guī)定的，通過以指定的速率累積的形式由NCO產(chǎn)生一個正弦波然后用一個相位的值來定位一個正弦調制ROM表的值。因此，NCO本質上用一個正弦波和用NCO的上升或下降沿輸出參考取樣時鐘對其取樣。圖4表示在時間和頻率域里NCO的處理。注意到這個表示并非量子化假設。</p><p>　　基于頻率控制字的裝載，NCO在一個時期

90、內(nèi)提供一批幅度的輸出值。這個正弦曲線的頻率域表示在指定的頻率里是一個推動的作用。NCO在NCO參考時鐘速率下輸出這個正弦曲線的離散數(shù)字取樣。在時間域里，NCO輸出是一個取樣時鐘邊緣閘門乘于正弦波形式產(chǎn)生的一個推動序列正弦振幅的作用。在頻率域里，參考時鐘的取樣產(chǎn)生一系列在K倍的NCO時鐘頻率脈沖（當K=...-1，2，1，2....）。當在時間域里取樣時鐘乘于正弦曲線，正弦曲線頻率域成分和取樣時鐘需要卷積來產(chǎn)生NCO輸出頻率域表示的NCO

91、輸出。</p><p>　　頻率域的結果是在正弦曲線基本頻率的脈沖作用和別的脈沖作用發(fā)生在K倍的NCO時鐘頻率加上或減去基本頻率?；镜暮蛣e的成分發(fā)生在：</p><p>　　K*Fclk - Fout</p><p>　　K*Fclk + Fout</p><p>　　當K = ... -1, 0 , 1, 2 ..... 和 K = 0是

92、NCO正弦曲線基本頻率。</p><p>　　Fout是指定的NCO正弦曲線輸出頻率</p><p>　　Fclk是NCO參考時鐘頻率</p><p>　　DDS系統(tǒng)中的DAC提取NCO的輸出值并轉化他們的值為模擬電壓。圖4顯示出時間和頻率域DAC過程開始于NCO的輸出的表示。DAC輸出是一個抽樣和保持那些NCO數(shù)字幅度控制字和轉換那些值為一個模擬電壓和保持那些值為

93、一個抽樣時鐘周期的電路。DAC過程的時域結構是NCO抽樣輸出值和一個抽樣周期脈沖的卷積。抽樣脈沖的頻率域結構是一個sin(x)/x功能和在抽樣時鐘頻率的第一個零。因為時域是卷積的，頻率域就是相當于相乘。這個乘法過程使得NCO輸出有一個sin(x)/x包絡。這個在DAC輸出的衰減在下面計算出來而且一個抽樣輸出頻譜。</p><p>　　Atten(F) = 20log[(sin(pF/Fclk)/pF/Fclk)]

94、當F是輸出頻率， Fclk是抽樣時鐘頻率</p><p>　　根據(jù)取樣理論，實際的值量子化為數(shù)字形式必須考慮一個DDS系統(tǒng)的性能分析。一個DDS系統(tǒng)的假的響應是主要由兩個量子化參量確定的。這些參量是相位累加器的相位量子化和ROM正弦曲線表和DAC的量子化量級。</p><p>　　如上所示，相位累加器只有

95、高Y比特是用來尋址ROM表。值得注意的是，僅用高Y位引入一個相位截短。當一個頻率控制字包含一個非零的值在低（N-Y-1：0）位是裝載到DDS系統(tǒng)的，低非零位累加到高Y位和使得產(chǎn)生一個相位截短。相位的截短出現(xiàn)的頻率可以根據(jù)以下計算：</p><p>　　Ftrunc = FW(N-Y-1:0)/2N-Y * Fclk.</p><p>　　一個相位的截短會周期性（以Ftrunc速率）相位調制

96、輸出載波提前2p/28來補償頻率控制字間隔多于/2Y。相位的跳轉由相位截短位累加在基波周圍產(chǎn)生突刺。</p><p>　　這些突刺位于基頻的正和負截短頻率，突刺的大小是20log(2Y)dBc。一個相位截短突刺輸出的例子如圖5所示。</p><p>　　在一個典型的NCO設計里，正弦ROM表會保持一個1/4正弦波（0，Pi/2）的量級。ROM表是通過把所有可能的相位值地址和映射到實際正弦波

97、大小的近似D比特來產(chǎn)生的。因此，最大的輸出誤差為?-½ LSB（假設當突刺為-20log(2D)dBc的最壞情況時）。</p><p>　　類似于NCO的ROM表，一個DAC也同樣是這樣量子化數(shù)字值為模擬值的。一個DAC輸出的模擬電壓取決于輸入的數(shù)字值。當設計NCO正弦ROM表時，一種方法是根據(jù)經(jīng)驗好于通過理解ROM表和DAC之間的交互作用而在DAC線性得出一些數(shù)據(jù)。DAC的量化曲線數(shù)字輸入對應模擬輸出

98、的DAC量化曲線可以看作是理想線性的。微分線性和積分線性這兩個線性參數(shù)通常是用來衡量DAC性能。</p><p>　　微分線性是指輸出的步進大小為比特到比特。一個DAC必須編碼一個最大的1LSB微分線性。當輸入碼增加，DAC的輸出必須相應增加。假如DAC電壓的增加不是對應于一個增加的輸入數(shù)字值，可以說DAC是缺碼的。因此，一個有大于1LSB微分線性的10比特DAC可以精確到9或者更小的比特。精確輸出的比特數(shù)量會導

99、致DDS當dl是微分線性的比特數(shù)量時的虛假的性能-20log(2dl)。</p><p>　　積分線性是一個DAC的總的線性性能對一個理想的線性直線的一個衡量。那條直線圖當DC偏置可能是DAC的最大或者最小時可以看作“最好的直線”，或者那條直線可以穿過輸出的最大和最小值的結束點。超出輸出范圍時一個DAC會有一個特有的彎曲特性曲線。根據(jù)曲線的形狀和對稱度（半個DAC輸出的周期對稱），就可以產(chǎn)生DDS基本輸出頻率的輸