外文翻譯及原文翻譯--咨詢(xún)應(yīng)用工程師- 33關(guān)于直接數(shù)字頻率合成器的問(wèn)題

1、<p>　　本科畢業(yè)設(shè)計(jì)（論文）外文翻譯譯文</p><p>　　學(xué)生姓名： 王 惠 </p><p>　　院 （系）： 電子工程學(xué)院儀器系 </p><p>　　專(zhuān)業(yè)班級(jí)： 測(cè)控0701 </p><p>　　指導(dǎo)教師： 劉

2、選 朝 </p><p>　　完成日期： 20 11 年 3 月 7 日 </p><p>　　咨詢(xún)應(yīng)用工程師- 33關(guān)于直接數(shù)字頻率合成器的問(wèn)題</p><p>　　作者 Eva Murphy [eva.murphy@analog.com]</p><p>　　Colm Slattery [col

3、m.slattery@analog.com]</p><p>　　什么是直接數(shù)字頻率合成器？ 直接數(shù)字頻率合成器（DDS）是一種產(chǎn)生模擬波形（通常是正弦波）的儀器，這種儀器是生成一個(gè)數(shù)字形式的時(shí)變信號(hào)，然后執(zhí)行數(shù)字到模擬的轉(zhuǎn)換。因?yàn)橛靡粋€(gè)DDS設(shè)備操作主要是數(shù)字形式，所以它可以提供輸出頻率之間的快速轉(zhuǎn)換，較高的頻率分辨率并且可以在一個(gè)寬頻帶上進(jìn)行操作。隨著設(shè)計(jì)和工藝技術(shù)的進(jìn)步，現(xiàn)在的DDS器件都非常小巧

4、，在低功率下也可以工作。 </p><p>　　為什么我們要使用直接數(shù)字頻率合成器（DDS）？難道就沒(méi)有其他產(chǎn)生頻率的簡(jiǎn)單方法嗎？ 能夠準(zhǔn)確地產(chǎn)生和控制各種頻率和輪廓的波形的能力已成為一個(gè)通用于多個(gè)行業(yè)重要要求。在通信系統(tǒng)中能否利用良好的雜散性提供低相位噪聲可變頻率的活躍來(lái)源，或僅產(chǎn)生用于工業(yè)或生物醫(yī)學(xué)測(cè)試設(shè)備的應(yīng)用的頻率刺激，便利、簡(jiǎn)潔和低成本是重要的設(shè)計(jì)考慮因素。頻率產(chǎn)生的多種可能性對(duì)設(shè)計(jì)師來(lái)說(shuō)是開(kāi)

5、放的，從鎖相回路（PLL）——極高頻率合成的基礎(chǔ)技術(shù)，到以數(shù)模轉(zhuǎn)換器（DAC）的動(dòng)態(tài)編制程序輸出來(lái)產(chǎn)生低頻任意波形。但是DDS技術(shù)迅速在解決頻率（或波形）產(chǎn)生的通信和工業(yè)應(yīng)用要求上得到接受，因?yàn)閱涡酒呻娐菲骷梢院?jiǎn)單的產(chǎn)生可編程模擬輸出波形，具有較高的分辨率和精度。此外，在這兩種工藝技術(shù)和設(shè)計(jì)的不斷改進(jìn)也使得成本和功耗較從前降低了許多。例如，AD9833——基于DDS的可編程波形發(fā)生器（圖1）在5.5 V的電壓下工作工作具有25 M

6、Hz的時(shí)鐘，消耗的最大功率為30毫瓦。</p><p>　　圖1 單片波形發(fā)生器</p><p>　　使用直接數(shù)字頻率合成器（DDS）的主要優(yōu)點(diǎn)有哪些？ 像AD9833 之類(lèi)的DDS器件都可通過(guò)一個(gè)高速串行外設(shè)接口（SPI）進(jìn)行編程，并且只需要一個(gè)外部時(shí)鐘來(lái)生成簡(jiǎn)單的正弦波。 DDS器件，現(xiàn)已能產(chǎn)生頻率從不到1赫茲到高達(dá)400兆赫（以1GHz的時(shí)鐘為準(zhǔn)）。其低功耗，低成本，單一小

7、包裝，固有的優(yōu)良性能和能對(duì)輸出波形的進(jìn)行數(shù)字編程（和重新計(jì)劃）的能力相結(jié)合的特點(diǎn)使DDS器件成為非常吸引人的解決方案，比包括離散元素的聚合的不太靈活的解決方案更好。</p><p>　　哪種輸出才能生成一個(gè)典型的DDS的設(shè)備？ DDS器件不僅限于單純的正弦波輸出。圖2顯示了由AD9833產(chǎn)生的方、三角和正弦輸出。</p><p><b>　　Listen</b>

8、;</p><p>　　Read phonetically</p><p>　　Dictionary - View detailed dictionary</p><p>　　圖2 DDS的方波、三角波、正弦波輸出</p><p>　　DDS的設(shè)備如何產(chǎn)生正弦波？ 下面是一個(gè)DDS器件的內(nèi)部電路故障：其主要組成是相位累加器，相幅轉(zhuǎn)換

9、方法（通常是通過(guò)正弦查找表）和一個(gè)數(shù)模轉(zhuǎn)換器。這些區(qū)塊入圖3所示。</p><p><b>　　Listen</b></p><p>　　圖3 直接數(shù)字頻率合成器組成框圖</p><p>　　直接數(shù)字頻率合成器產(chǎn)生一個(gè)給定頻率的正弦波。頻率取決于兩個(gè)變量，參考時(shí)鐘頻率和編入頻率寄存器的二進(jìn)制數(shù)（控制字）。 頻率寄存器中的二進(jìn)制數(shù)提供

10、了相位累加器的主要輸入。在使用正弦查找表時(shí)，相位累加器為查找表計(jì)算相位（角）的地址，它輸出相角的正弦相應(yīng)的幅度數(shù)字值至數(shù)字模擬轉(zhuǎn)換器。反過(guò)來(lái)數(shù)字模擬轉(zhuǎn)換器將這個(gè)數(shù)字轉(zhuǎn)換為模擬電壓或電流的相應(yīng)值。要生成一個(gè)固定頻率的正弦波，需要給每個(gè)時(shí)鐘周期的相位累加器一個(gè)定值（相位增量決定于二進(jìn)制數(shù)）。如果相位增量很大，相位累加器會(huì)加速正弦查找表過(guò)程，從而產(chǎn)生一個(gè)高頻率的正弦波。如果相位增量很小，相位累加器將進(jìn)行更多的步驟，因此產(chǎn)生波形較慢。</

11、p><p>　　一個(gè)完整的數(shù)字模擬轉(zhuǎn)換器是什么意思？ 將D / A轉(zhuǎn)換器和DDS集成到一個(gè)芯片上稱(chēng)為一個(gè)完整的DDS解決方案，對(duì)所有 DDS器件均通用。 讓我們進(jìn)一步談一談相位累加器。它是如何工作的？ 連續(xù)時(shí)間正弦信號(hào)具有0至2重復(fù)的固定相值范圍。數(shù)字實(shí)現(xiàn)過(guò)程相同。計(jì)數(shù)器攜帶的功能允許相位累加器在DDS過(guò)程作為一個(gè)相輪。要理解這個(gè)基本功能，我們將正弦波振蕩設(shè)想為一個(gè)繞圓圈旋轉(zhuǎn)的矢量（見(jiàn)圖4）。

12、相輪上的指定點(diǎn)對(duì)應(yīng)正弦波的等效點(diǎn)。由于矢量左右相輪轉(zhuǎn)動(dòng)，設(shè)想該角的正弦值產(chǎn)生相應(yīng)的輸出正弦波。矢量以恒定的速度圍繞相輪的一個(gè)循環(huán)，形成一個(gè)輸出正弦波的完整周期。相位累加器提供隨相輪線性轉(zhuǎn)動(dòng)向量的等距相位角值。相位累加器的內(nèi)容對(duì)應(yīng)于輸出正弦波循環(huán)的主要點(diǎn)。 </p><p><b>　　圖4 數(shù)字相輪</b></p><p>　　相位累加器實(shí)際上是一個(gè)模- M的計(jì)數(shù)器

13、，存儲(chǔ)數(shù)量增加一次，接收一次時(shí)鐘脈沖。遞增量級(jí)是由二進(jìn)制輸入編碼字決定（M）。這個(gè)字在參考時(shí)鐘更新之間形成相位步長(zhǎng)，有效地設(shè)置需要跳過(guò)的相輪點(diǎn)的數(shù)量。階躍越大，相位累加器溢出越快并能完成與之等效的一個(gè)正弦波周期。</p><p>　　相輪上的離散點(diǎn)的數(shù)量是由相位累加器（N）的分辨率決定，這也就決定了直接數(shù)字頻率合成器的調(diào)諧分辨率。對(duì)于n = 28位，M值為0000 ... 0001的相位累加器，將使228個(gè)參考時(shí)

14、鐘周期（增量）后的增量溢出相位累加器。如果M值改為0111 ... 1111，相位累加器只在2個(gè)參考時(shí)鐘周期后溢出（奈奎斯特定理要求的最低限度）。此關(guān)系是在直接數(shù)字頻率合成器結(jié)構(gòu)的基本方程中發(fā)現(xiàn)的： </p><p><b>　　其中：</b></p><p>　　fOUT= 直接數(shù)字頻率合成器的輸出頻率</p><p>　　M =二進(jìn)制諧調(diào)字

15、 fc=內(nèi)部參考時(shí)鐘頻率（系統(tǒng)時(shí)鐘） n=每組相位累加器的長(zhǎng)度，用位量度 </p><p>　　M值的變化引起輸出頻率直接和相位連續(xù)的變化。鎖相環(huán)中無(wú)環(huán)路建立時(shí)間。由于輸出頻率的增加，每個(gè)周期的樣本數(shù)量減少。由于采樣定律決定了每個(gè)周期至少有兩次采樣才能重建輸出波形，最大的DDS輸出頻率為FC/ 2。然而實(shí)際應(yīng)用中，為了提高重建波形的質(zhì)量并對(duì)輸出進(jìn)行濾波，輸出頻率一般小于FC/ 2。當(dāng)頻率恒定時(shí)

16、，相位累加器的輸出呈線性增加，所以它產(chǎn)生的模擬波形是一個(gè)斜坡。</p><p>　　那么線性輸出如何轉(zhuǎn)換成正弦波呢？ 一個(gè)幅相查找表用于轉(zhuǎn)換相位累加器的瞬時(shí)輸出值（28 AD9833位）它將正弦波的振幅信息，傳給（10位）的D / A轉(zhuǎn)換器。 DDS的組成充分利用正弦波的對(duì)稱(chēng)性和映射邏輯將累加器中四分之一的正弦波合成為一個(gè)完整的正弦波。相幅查找表通過(guò)通過(guò)從前向后瀏覽查找表的產(chǎn)生剩余數(shù)據(jù)。這個(gè)過(guò)程形象地呈現(xiàn)

17、在圖5中。</p><p>　　圖5 信號(hào)在DDS系統(tǒng)中的流經(jīng)途徑</p><p>　　DDS的普遍用途是什么？ 目前使用的基于DDS的波形發(fā)生器的應(yīng)用程序主要為以下兩種主要類(lèi)型：通訊系統(tǒng)設(shè)計(jì)人員需要活躍（即立即響應(yīng)）的具有好的相位噪聲性能的頻率資源并且低雜散頻率源往往選擇其光譜性能和頻率調(diào)諧分辨率相結(jié)合的DDS 。這些應(yīng)用包括用DDS進(jìn)行調(diào)制、作為參考鎖相環(huán)來(lái)提高整體頻率可調(diào)

18、性，作為本地振蕩器（LO），甚至可以作為直接的射頻傳輸。 另外，許多工業(yè)和醫(yī)學(xué)領(lǐng)域?qū)DS作為一個(gè)可編程的波形發(fā)生器。因?yàn)镈DS是數(shù)字可編程的，波形的相位和頻率可以很容易調(diào)整，而不像傳統(tǒng)的模擬程控波形發(fā)生器需改變外部元件。 DDS在實(shí)時(shí)控制時(shí)允許簡(jiǎn)單的頻率調(diào)整來(lái)定位諧振的頻率或補(bǔ)償溫度漂移。 這些應(yīng)用包括在可調(diào)頻率源中使用DDS來(lái)測(cè)量阻抗（例如在基于阻抗的傳感器中），為微刺激產(chǎn)制造脈沖波調(diào)制信號(hào)或檢查局域網(wǎng)或電話(huà)電纜中是否有

19、衰減。 你認(rèn)為對(duì)于設(shè)備和系統(tǒng)的設(shè)計(jì)者們DDS的關(guān)鍵優(yōu)勢(shì)是什么？ 當(dāng)今成本低、高性能、功能集成的DDS芯片廣泛應(yīng)用在通訊系統(tǒng)和傳感器領(lǐng)域。他們吸引設(shè)計(jì)工程師的優(yōu)勢(shì)包括： ?數(shù)字控制微赫茲的頻率調(diào)整和副級(jí)逐步優(yōu)化功能， ?調(diào)整輸出</p><p>　　怎樣使用DDS的設(shè)備進(jìn)行頻移鍵控（FSK）編碼？ 二進(jìn)制頻移鍵控（通常簡(jiǎn)稱(chēng)為FSK）的是最簡(jiǎn)單的數(shù)據(jù)編碼形式之一。通過(guò)將連續(xù)載波

20、頻率移到二分之一（此后均為二進(jìn)制）離散頻率來(lái)傳輸數(shù)據(jù)。頻率F1（或許更高）為標(biāo)志頻率（二進(jìn)制1），F(xiàn)0為空間頻率（二進(jìn)制0）。圖6顯示了標(biāo)記空間數(shù)據(jù)和傳輸信號(hào)之間關(guān)系的例子。</p><p><b>　　Listen</b></p><p>　　圖6 頻移鍵控調(diào)制</p><p>　　這種編碼方案用DDS很容易實(shí)現(xiàn)。代表輸出頻率的DDS頻率控

21、制字生成F0和F1，因?yàn)樗鼈冊(cè)?和1模式時(shí)進(jìn)行傳輸。用戶(hù)在傳數(shù)據(jù)之前將兩個(gè)調(diào)整字編入儀器。在AD9834的條件下，兩個(gè)頻率寄存器便于FSK編碼。在設(shè)備上（FSELECT）的專(zhuān)用針接受調(diào)制信號(hào)并選擇適當(dāng)?shù)目刂谱郑ɑ蝾l率寄存器）。圖7演示了的FSK編碼的實(shí)現(xiàn)框圖。</p><p>　　圖7 基于DDS的頻移鍵控編碼器</p><p>　　PSK編碼的實(shí)現(xiàn)過(guò)程又是如何呢？ 相移鍵控（P

22、SK）是另一種數(shù)據(jù)編碼的簡(jiǎn)單形式。在PSK過(guò)程中載波頻率保持不變，通過(guò)傳輸信號(hào)的相位變化來(lái)傳輸信息。完成PSK的方法中，最簡(jiǎn)單的是二進(jìn)制BPS碼（BPSK），它僅需要兩個(gè)信號(hào)相位：0度和180度。BPSK編碼相移0為邏輯1輸入，180為邏輯0輸入。每個(gè)位的狀態(tài)由前一位的狀態(tài)決定。如果波相位不改變，信號(hào)狀態(tài)保持不變（低或高）。如果波相位反轉(zhuǎn)（180度的變化），那么信號(hào)狀態(tài)變化（從低到高或從高向低）。</p><p>

23、;　　PSK的編碼用DDS芯片很容易實(shí)現(xiàn)。大多數(shù)的設(shè)備是單獨(dú)的輸入寄存器（相位寄存器），可以分別載入一個(gè)相位值。這個(gè)值直接添加到載波相位，不會(huì)改變其頻率。通過(guò)改變?cè)摷拇嫫鞯膬?nèi)容來(lái)調(diào)變載波相位，從而產(chǎn)生PSK的輸出信號(hào)。對(duì)于需要高速調(diào)制的應(yīng)用，AD9834用專(zhuān)用切換輸入引腳（PSELECT）來(lái)選擇預(yù)載相位寄存器，這需要在寄存器和調(diào)控的載體之間選擇。 更復(fù)雜的PSK形式采用四或八個(gè)波階段。這使二進(jìn)制數(shù)據(jù)以每相變比BPSK調(diào)制更快的速

24、度傳播成為可能。在四相調(diào)制（正交PSK或QPSK）可能的相角為0、+90、-90和180度，每相移可以代表兩個(gè)信號(hào)因子。AD9830，AD9831，AD9832和AD9835有四個(gè)相位寄存器，它們通過(guò)給寄存器持續(xù)更新不同的相位偏移來(lái)執(zhí)行復(fù)雜的調(diào)制方案。</p><p>　　多個(gè)DDS器件可以實(shí)現(xiàn)如智商能力的同步嗎？ 用運(yùn)行在相同主時(shí)鐘上的兩個(gè)單DDS器件輸出兩個(gè)可直接控制相位關(guān)系的信號(hào)是可以實(shí)現(xiàn)的。在圖8

25、中，兩個(gè)AD9834使用一個(gè)參考時(shí)鐘進(jìn)行編程并用相同的復(fù)位引腳同時(shí)更新兩個(gè)部分。使用這個(gè)裝置可以實(shí)現(xiàn)IQ調(diào)制。</p><p>　　圖8 多個(gè)DDS芯片的同步模式</p><p>　　置電和傳輸數(shù)據(jù)之前必須復(fù)位。這使得DDS輸出已知相位，它作為共同的參照點(diǎn)實(shí)現(xiàn)多個(gè)DDS器件同步。當(dāng)新的數(shù)據(jù)同時(shí)發(fā)送到多個(gè)DDS單元時(shí)，它可以使相位關(guān)系保持一致，并且它們的相對(duì)相移可以通過(guò)相移寄存器目的性的轉(zhuǎn)

26、移。 AD9833和AD9834的相位分辨率有12位，有效分辨率為0.1度。 [有關(guān)多個(gè)DDS單元同步詳情請(qǐng)參閱應(yīng)用筆記AN - 605。]</p><p>　　基于DDS系統(tǒng)的主要性能指標(biāo)是什么？ 相位噪聲、抖動(dòng)和無(wú)雜散動(dòng)態(tài)范圍（SFDR）。</p><p>　　相位噪聲是用來(lái)衡量振蕩器的短期頻率不穩(wěn)定性（dBc / Hz）。據(jù)測(cè)定頻率變化引起的單邊帶噪音在振蕩器的工作頻率下有兩

27、個(gè)或更多的頻移（以下振蕩器的工作頻率在均為1 Hz）。這種測(cè)量方法已用在模擬通信行業(yè)的特殊應(yīng)用上。</p><p>　　DDS器件是否具有良好的相位噪聲？ 采樣系統(tǒng)中的噪音取決于許多因素。參考時(shí)鐘抖動(dòng)是DDS系統(tǒng)中的基本信號(hào)的相位噪聲，相位截?cái)嗫赡芤脲e(cuò)誤的級(jí)別，這根據(jù)碼字選擇而定。對(duì)于完全由截?cái)喽M(jìn)制編碼字表示的比率是沒(méi)有截?cái)嗾`差的。需要更多的比特率時(shí)，所產(chǎn)生的相位噪聲截?cái)嗾`差表現(xiàn)在光譜圖的尖峰上。他們

28、的大小和分布取決于選擇的代碼字。DAC也會(huì)引入噪聲。 DAC的量化或線性誤差會(huì)產(chǎn)生噪聲和諧波。圖9顯示了AD9834下DDS典型的相位噪聲圖。</p><p>　　圖9 AD9834的典型輸出相位噪聲曲線（輸出頻率為2 MHz，M的時(shí)鐘是50兆赫）</p><p>　　什么是抖動(dòng)呢？ 抖動(dòng)是數(shù)字信號(hào)邊沿的動(dòng)態(tài)位移偏離平衡位置的程度，用均方根來(lái)衡量。一個(gè)完美的振蕩器的上升和下降沿時(shí)

29、間是精確發(fā)生的，絕不會(huì)變化。這當(dāng)然是不可能的，因?yàn)榧词棺詈玫恼袷幤饕彩怯珊性胍粼春推渌蓴_的實(shí)際部件組成的。高品質(zhì)，低相位噪聲的晶體振蕩器在超過(guò)幾百萬(wàn)時(shí)鐘邊沿積累下的抖動(dòng)小于35皮秒（ps）。</p><p>　　振蕩器中的抖動(dòng)由熱噪聲造成，振蕩器中電子不穩(wěn)定，外部干擾通過(guò)電源軌，地面，甚至輸出進(jìn)入系統(tǒng)。其他干擾包括外部磁場(chǎng)或電場(chǎng)如射頻發(fā)射器附近的干擾，這將使抖動(dòng)影響振蕩器的輸出。即使是一個(gè)簡(jiǎn)單的放大器、變頻器

30、或緩沖區(qū)都會(huì)引起抖動(dòng)信號(hào)。</p><p>　　因此一個(gè)DDS設(shè)備輸出增加一定的抖動(dòng)信號(hào)。由于每個(gè)時(shí)鐘已經(jīng)有抖動(dòng)，選擇一個(gè)低抖動(dòng)振蕩器是至關(guān)重要的開(kāi)始。劃分一個(gè)高頻時(shí)鐘頻率是減少抖動(dòng)的一種方法。隨著頻率的劃分，相同數(shù)量的抖動(dòng)發(fā)生的時(shí)間更長(zhǎng)，這降低其在系統(tǒng)時(shí)間中的比例。</p><p>　　一般情況下，為了減少抖動(dòng)來(lái)源并避免引入額外的噪聲，應(yīng)該使用一個(gè)穩(wěn)定的參考時(shí)鐘，避免使用信號(hào)和電路轉(zhuǎn)換慢

31、，使用頻率最高的參考頻率，以便增加采樣。</p><p>　　無(wú)雜散動(dòng)態(tài)范圍（SFDR）是指最高基本信號(hào)和最高噪聲信號(hào)的之間的比率（以分貝衡量），該信號(hào)包括頻譜中最高的相關(guān)頻率和諧波成分。要保證SFDR的值最合適必須用好的振蕩器。</p><p>　　在與其他通信通道和應(yīng)用程序共享的頻譜應(yīng)用中SFDR是重要的性能指標(biāo)。如果發(fā)送器的輸出發(fā)送到其它頻段就可能會(huì)損壞或中斷鄰近的信號(hào)。</p

32、><p>　　典型的主時(shí)鐘為50- MHz的AD9834（10位DDS）輸出如圖10所示。在（a）圖中，輸出頻率正好是1/3主時(shí)鐘頻率（MCLK）。由于頻率的正確選擇，25兆赫窗口下的頻率無(wú)諧波，也稱(chēng)最小化，所有波峰信號(hào)都在80分貝以下（SFDR= 80分貝）。（b）中低頻情況下波形含有更多的點(diǎn)（但對(duì)于理想波形并不足夠，），并給出了一個(gè)更真實(shí)的圖，第二個(gè)諧波頻的最大沖擊大約是50分貝（SFDR=50分貝）。Liste

33、nWú zá sǎn dòngtài fànwéi (SFDR) shì zhǐ bǐ (yǐ fēnbèi héngliáng) zhī jiān de jīběn xìnhào de zuìgāo shuǐpíng, rènhé xūjiǎ de, xình

34、4;o, bāokuò zuìgāo jíbié de biémíng xiāngguān de pínlǜ héxié bō chéngfèn, zài pínpǔ. Duìyú zuì hǎo de SFDR, bìxū yī kāishǐ jiù yǒu

35、 yīgè gāo pǐnzhí de zhèndàng qì.</p><p>　　圖10 輸出的AD9834具有50 MHz的主時(shí)鐘</p><p>　　(a) fOUT = 16.667 MHz (i.e., MCLK/3); (b) fOUT = 4.8 MHz</p><p>　　你有更容易進(jìn)行編程和預(yù)測(cè)

36、DDS性能的工具嗎？ 在線互動(dòng)設(shè)計(jì)工具是選擇控制字的得力助手，需要給定一個(gè)參考時(shí)鐘和所需的輸出頻率和/或相位。選擇所需的頻率，待外部濾波器重建后諧波和理想化輸出。例如圖11所示。表格數(shù)據(jù)也提供了主要的圖像和諧波。</p><p><b>　　Listen</b></p><p>　　圖11 屏幕演示互動(dòng)式設(shè)計(jì)工具，一個(gè)sinx/ x的典型設(shè)備的輸出圖形<

37、;/p><p>　　Nǐ yǒu gōngjù, shǐ rénmen gèng róngyì jìnxíng biānchéng hé yùcè DDS de biǎoxiàn?Zài wǎngshàng hùdòng shèjì gō

38、ngjù shì xuǎnzé tiáozhěng dehuà zhùshǒu, gěi dìng yīgè cānkǎo shízhōng hé suǒ xū de shūchū pínlǜ hé/huò jiēduàn. Xuǎnzé suǒ xū de pínlǜ, xi&

39、#233; bō hé lǐxiǎng huà de shūchū hòu xiǎnshì wàibù chóngjiàn flter dédào le yìngyòng. Yīgè lìzi shì rú tú 11 suǒ shì. Biǎogé

40、 shùjù yě tígōng le zhǔyào de túxiàng héxié bō.</p><p>　　Dictionary - View detailed dictionary</p><p>　　Dictionary - View detailed dictionary</p>&

41、lt;p>　　怎樣利用這些工具對(duì)DDS進(jìn)行編程？ 僅需要要求的頻率輸出和系統(tǒng)的參考時(shí)鐘頻率。該設(shè)計(jì)工具將輸出全部程序。以圖12為例，MCLK為25兆赫茲所需的輸出頻率為10兆赫茲。一旦啟動(dòng)按鈕，完整程序的一部分就包含在初始化進(jìn)程中。 </p><p><b>　　圖12. 窗體頂端</b></p><p>　　圖12 典型的編程序列演示</p&g

42、t;<p>　　怎樣評(píng)價(jià)DDS器件？ 所有已購(gòu)買(mǎi)的DDS器件都有一個(gè)評(píng)估板。攜帶在專(zhuān)用軟件中，用戶(hù)在幾分鐘內(nèi)就能進(jìn)行測(cè)試/評(píng)估。每一個(gè)包含評(píng)估板的技術(shù)說(shuō)明都有圖示，并展示了最佳的電路板設(shè)計(jì)和布局。</p><p><b>　　Listen</b></p><p>　　Ask The Application Engineer—33All About

43、 Direct Digital Synthesis</p><p>　　By Eva Murphy [eva.murphy@analog.com]</p><p>　　Colm Slattery [colm.slattery@analog.com]</p><p>　　What is Direct Digital Synthesis?</p><

44、p>　　Direct digital synthesis (DDS) is a method of producing an analog waveform—usually a sine wave—by generating a time-varying signal in digital form and then performing a digital-to-analog conversion. Because operat

45、ions within a DDS device are primarily digital, it can offer fast switching between output frequencies, fne frequency resolution, and operation over a broad spectrum of frequencies. With advances in design and process te

46、chnology, today’s DDS devices are very compact and draw little powe</p><p>　　Why would one use a direct digital synthesizer (DDS)? Aren’t there other methods for easily generating frequencies?</p><

47、;p>　　The ability to accurately produce and control waveforms of various frequencies and profles has become a key requirement common to a number of industries. Whether providing agile sources of low-phase-noise variabl

48、e-frequencies with good spurious performance for communications, or simply generating a frequency stimulus in industrial or biomedical test equipment applications, convenience, compactness, and low cost are important des

49、ign considerations.Many possibilities for frequency generation are o</p><p>　　What are the main benefts of using a DDS?</p><p>　　DDS devices like the AD9833 are programmed through a high speed s

50、erial peripheral-interface (SPI), and need only an external clock to generate simple sine waves. DDS devices are now available that can generate frequencies from less than 1 Hz up to 400 MHz (based on a 1-GHz clock). The

51、 benefts of their low power, low cost, and single small package, combined with their inherent excellent performance and the ability to digitally program (and re-program) the output waveform, make DDS devices an extr</

52、p><p>　　What kind of outputs can I generate with a typical DDS device?</p><p>　　DDS devices are not limited to purely sinusoidal outputs. Figure 2 shows the square-, triangular-, and sinusoidal out

53、puts available from an AD9833.</p><p>　　How does a DDS device create a sine wave? </p><p>　　Here’s a breakdown of the internal circuitry of a DDS device: its main components are a phase accumula

54、tor, a means of phase-to-amplitude conversion (often a sine look-up table), and a DAC. These blocks are represented in Figure 3.</p><p>　　A DDS produces a sine wave at a given frequency. The frequency depend

55、s on two variables, the reference-clock frequency and the binary number programmed into the frequency register (tuning word).</p><p>　　The binary number in the frequency register provides the main input to t

56、he phase accumulator. If a sine look-up table is used, the phase accumulator computes a phase (angle) address for the look-up table, which outputs the digital value of amplitude—corresponding to the sine of that phase an

57、gle—to the DAC. The DAC, in turn, converts that number to a corresponding value of analog voltage or current. To generate a fixed-frequency sine wave, a constant value (the phase increment—which is determined</p>

58、<p>　　What do you mean by a complete DDS? </p><p>　　The integration of a D/A converter and a DDS onto a single chip is commonly known as a complete DDS solution, a property common to all DDS devices fro

59、m ADI.</p><p>　　Let’s talk some more about the phase accumulator. How does it work? </p><p>　　Continuous-time sinusoidal signals have a repetitive angular phase range of 0 to 2. The digital imp

60、lementation is no different. The counter’s carry function allows the phase accumulator to act as a phase wheel in the DDS implementation.</p><p>　　To understand this basic function, visualize the sine-wave o

61、scillation as a vector rotating around a phase circle (see Figure 4). Each designated point on the phase wheel corresponds to the equivalent point on a cycle of a sine wave. As the vector rotates around the wheel, visual

62、ize that the sine of the angle generates a corresponding output sine wave. One revolution of the vector around the phase wheel, at a constant speed, results in one complete cycle of the output sine wave. The phase accumu

63、</p><p>　　The phase accumulator is actually a modulo-M counter that increments its stored number each time it receives a clock pulse. The magnitude of the increment is determined by the binary-coded input wo

64、rd (M). This word forms the phase step size between reference-clock updates; it effectively sets how many points to skip around the phase wheel. The larger the jump size, the faster the phase accumulator overfows and com

65、pletes its equivalent of a sine-wave cycle. The number of discrete phase points con</p><p><b>　　where: </b></p><p>　　fOUT = output frequency of the DDS </p><p>　　M = b

66、inary tuning word </p><p>　　fC = internal reference clock frequency (system clock) n = length of the phase accumulator, in bits</p><p>　　Changes to the value of M result in immediate and phase-c

67、ontinuous changes in the output frequency. No loop settling time is incurred as in the case of a phase-locked loop.</p><p>　　As the output frequency is increased, the number of samples per cycle decreases. S

68、ince sampling theory dictates that at least two samples per cycle are required to reconstruct the output waveform, the maximum fundamental output frequency of a DDS is fC/2. However, for practical applications, the outpu

69、t frequency is limited to somewhat less than that, improving the quality of the reconstructed waveform and permitting fltering on the output. When generating a constant frequency, the output of the </p><p>　

70、　Then how is that linear output translated into a sine wave?</p><p>　　A phase-to-amplitude lookup table is used to convert the phase-accumulator’s instantaneous output value (28 bits for AD9833)—with unneede

71、d less-signifcant bits eliminated by truncation—into the sine-wave amplitude information that is presented to the (10-bit) D/A converter. The DDS architecture exploits the symmetrical nature of a sine wave and utilizes m

72、apping logic to synthesize a complete sine wave from one-quarter-cycle of data from the phase accumulator. The phase-to- amplitude lookup table</p><p>　　What are popular uses for DDS? </p><p>　　

73、Applications currently using DDS-based waveform generation fall into two principal categories: Designers of communications systems requiring agile (i.e., immediately responding) frequency sources with excellent phase noi

74、se and low spurious performance often choose DDS for its combination of spectral performance and frequency-tuning resolution. Such applications include using a DDS for modulation, as a reference for a PLL to enhance over

75、all frequency tunability, as a local oscillator (LO), or eve</p><p>　　Alternatively, many industrial and biomedical applications use a DDS as a programmable waveform generator. Because a DDS is digitally pro

76、grammable, the phase and frequency of a waveform can be easily adjusted without the need to change the external components that would normally need to be changed when using traditional analog-programmed waveform generato

77、rs. DDS permits simple adjustments of frequency in real time to locate resonant frequencies or compensate for temperature drift.</p><p>　　Such applications include using a DDS in adjustable frequency sources

78、 to measure impedance (for example in an impedance-based</p><p>　　sensor), to generate pulse-wave modulated signals for</p><p>　　micro-actuation, or to examine attenuation in LANs or</p>

79、<p>　　telephone cables.</p><p>　　What do you consider to be the key advantages of DDS to design-ers of real-world equipment and systems? </p><p>　　Today’s cost-competitive, high-performanc

80、e, functionally integrated DDS ICs are becoming common in both communication systems and sensor applications. The advantages that make them attractive to design engineers include:</p><p>　　? digitally contro

81、lled micro-hertz frequency-tuning and sub-degree phase-tuning capability,</p><p>　　? extremely fast hopping speed in tuning output frequency (or phase); phase-continuous frequency hops with no overshoot/unde

82、rshoot or analog-related loop settling-time anomalies, </p><p>　　? the digital architecture of DDS eliminates the need for the manual tuning and tweaking related to component aging and temperature drift in a

83、nalog synthesizer solutions, and</p><p>　　? the digital control interface of the DDS architecture facilitates an environment where systems can be remotely controlled and optimized with high resolution under

84、processor control.</p><p>　　How would I use a DDS device for FSK encoding? </p><p>　　Binary frequency-shift keying (usually referred to simply as FSK) is one of the simplest forms of data encodi

85、ng. The data is transmitted by shifting the frequency of a continuous carrier to one of two discrete frequencies (hence binary). One frequency, f1, (perhaps the higher) is designated as the mark frequency (binary one) an

86、d the other, f0, as the space frequency (binary zero). Figure 6 shows an example of the relationship between the mark-space data and the transmitted signal.</p><p>　　This encoding scheme is easily implemente

87、d using a DDS. The DDS frequency tuning word, representing the output frequencies, is set to the appropriate values to generate f0 and f1 as they occur in the pattern of 0s and 1s to be transmitted. The user programs the

88、 two required tuning words into the device before transmission. In the case of the AD9834, two frequency registers are available to facilitate convenient FSK encoding. A dedicated pin on the device (FSELECT) accepts the

89、modulating signal a</p><p>　　And how about PSK coding?</p><p>　　Phase-shift keying (PSK) is another simple form of data encoding. In PSK, the frequency of the carrier remains constant and the ph

90、ase of the transmitted signal is varied to convey the information. </p><p>　　Of the schemes to accomplish PSK, the simplest-known as binary PSK (BPSK)—uses just two signal phases, 0 degrees and 180 degrees.

91、BPSK encodes 0 phase shift for a logic 1 input and 180 phase shift for a logic 0 input. The state of each bit is determined according to the state of the preceding bit. If the phase of the wave does not change, the si

92、gnal state stays the same (low or high). If the phase of the wave reverses (changes by 180 degrees), then the signal state changes (from low to high, </p><p>　　PSK encoding is easily implemented with DDS ICs

93、. Most of the devices have a separate input register (a phase register) that can be loaded with a phase value. This value is directly added to the phase of the carrier without changing its frequency. Changing the content

94、s of this register modulates the phase of the carrier, thus generating a PSK output signal. For applications that require high speed modulation, the AD9834 allows the preloaded phase registers to be selected using a dedi

95、cated togglin</p><p>　　More sophisticated forms of PSK employ four- or eight- wave phases. This allows binary data to be transmitted at a faster rate per phase change than is possible with BPSK modulation. I

96、n four-phase modulation (quadrature PSK or QPSK), the possible phase angles are 0, +90, –90, and 180 degrees; each phase shift can represent two signal elements. The AD9830, AD9831, AD9832, and AD9835 provide four phase

97、registers to allow complex phase modulation schemes to be implemented by continuously updating d</p><p>　　Can multiple DDS devices be synchronized for, say, I-Q capability?</p><p>　　It is possib

98、le to use two single DDS devices that operate on the same master clock to output two signals whose phase relationship can then be directly controlled. In Figure 8, two AD9834s are programmed using one reference clock, wi

99、th the same reset pin being used to update both parts. Using this setup, it is possible to do I-Q modulation.</p><p>　　A reset must be asserted after power-up and prior to transferring any data to the DDS. T

100、his sets the DDS output to a known phase, which serves as the common reference point that allows synchronization of multiple DDS devices. When new data is sent simultaneously to multiple DDS units, a coherent phase relat

101、ionship can be maintained, and their relative phase offset can be predictably shifted by means of the phase-offset register. The AD9833 and AD9834 have 12 bits of phase resolution, with an eff</p><p>　　What

102、are the key performance specs of a DDS based system?</p><p>　　Phase noise, jitter, and spurious-free dynamic range (SFDR). Phase noise is a measure (dBc/Hz) of the short-term frequency instability of the osc

103、illator. It is measured as the single-sideband noise resulting from changes in frequency (in decibels below the amplitude at the operating frequency of the oscillator using a 1-Hz bandwidth) at two or more frequency disp