eda技術(shù)及軟件外文翻譯

1、<p>　　EDA Technology And Software</p><p>　　EDA is Electronic Design Automation (Electronic Automation) is the abbreviation of themselves, in the early 1990s from computer aided Design (CAD), computer ai

2、ded manufacturing (CAM), computer aided testing (CAT) and computer aided engineering (CAE) development of the concepts and come.</p><p>　　EDA technology is on the computer as the tool, the designer in EDA so

3、ftware platform, with VHDL HDL finish design documents, then by the computer automatically logic compilation, reduction, division, comprehensive, optimization, layout and wiring and simulation for a particular goal chips

4、, until the adapter compilation, logic mapping and programming download, etc.</p><p>　　1 EDA technology concepts</p><p>　　EDA technology is in electronic CAD technology developed on the basis of

5、 computer software system by means of computer for working platform, shirt-sleeve application of electronic technology, computer technology and information processing and intelligent technology to the latest achievements

6、 of electronic products, the automatic design.</p><p>　　Using EDA tools, electronic stylist can be from concept, algorithm, agreement, etc, begin to design your electronic system a lot work can be finished b

7、y computer and electronic products can be from circuit design, performance analysis to design the IC territory or PCB layout the whole process of the computer automatically complete the processing.</p><p>　　

8、Now on the concept of using EDA or category very wide. Included in machinery, electronics, communication, aerospace, chemical, mineral, biology, medicine, military and other fields, have EDA applications. Current EDA tec

9、hnology has in big companies, enterprises, institutions and teaching research departments extensive use. For example in the aircraft manufacturing process, from design, performance testing and characteristic analysis unt

10、il a flight simulator, all may involve EDA technology. Globa</p><p>　　EDA can be divided into system level and circuit-level and physical implementation level.</p><p>　　2. Development Environmen

11、t MAX + PLUSⅡ/ QUARTERⅡ </p><p>　　Altera Corporation is the world's three major CPLD / FPGA manufacturers of the devices it can achieve the highest performance and integration, not only because of the us

12、e of advanced technology and new logic structure, but also because it provides a modern design tools MAX + PLUSⅡprogrammable logic development software, the software is launched the third generation of Altera PLD develop

13、ment system. Nothing to do with the structure provides a design environment for Altera CPLD designers to easily</p><p>　　MAX + PLUSⅡdevelopment system has many outstanding features: </p><p>　?、?

14、open interface. </p><p>　　② design and construction related: MAX + PLUSⅡsupport Altera's Classic, ACEX 1K, MAX 3000, MAX 5000, MAX 7000, MAX 9000, FLEX 6000, FLEX 8000 and FLEX 10K series of programmable

15、 logic devices, gate count is 600 ~ 250 000 doors, offers the industry really has nothing to do with the structure of programmable logic design environment. MAX + PLUSⅡcompiler also provides a powerful logic synthesis an

16、d optimization to reduce the burden on the user's design. </p><p>　?、?can be run on multiple platforms: MAX + PLUSⅡsoftware PC-based WindowsNT 4.0, Windows 98, Win dows 2000 operating systems, but also i

17、n Sun SPARCstations, HP 9000 Series 700/800, IBM RISC System/6000 such as run on workstations. </p><p>　?、?fully integrated: MAX + PLUSⅡsoftware design input, processing, calibration functions are fully inte

18、grated within the programmable logic development tools, which can be debugged more quickly and shorten the development cycle. </p><p>　?、?modular tools: designers can input from a variety of design, editing,

19、 calibration and programming tools to choose the device to form a user-style development environment, when necessary, to retain on the basis of the original features to add new features. The MAX + PLUSⅡSeries supports a

20、variety of devices, designers need to learn new development tools for the development of new device structures. </p><p>　?、?mail-description language (HDL): MAX + PLUSⅡsoftware supports a variety of HDL desi

21、gn entry, including the standard VHDL, Verilog HDL and Altera's own developed hardware description language AHDL. </p><p>　?、?MegaCore Function: MegaCore are pre-validated for the realization of complex

22、system-level functions provided by the HDL netlist file. It ACEX 1K, MAX 7000, MAX 9000, FLEX 6000, FLEX 8000 and FLEX 10K devices provide the most optimal design. Users can purchase them from the Altera MegaCore, using

23、them can reduce the design task, designers can make more time and energy to improve the design and final product up. </p><p>　?、?OpenCore Features: MAX + PLUSⅡsoftware with open characteristics of the kernel

24、, OpenCore come to buy products for designers design their own assessment. </p><p>　　At the same time, MAX + PLUSⅡthere are many other design entry methods, including: </p><p>　　① graphic design

25、 input: MAX + PLUSⅡgraphic design input than other software easier to use features, because the MAX + PLUSⅡprovides a rich library unit for the designer calls, especially in the MAX2LIB in the provision of the mf library

26、 includes almost all 74 series of devices, in the prim library provides all of the separate digital circuit devices. So long as a digital circuit knowledge, almost no learning can take advantage of excess MAX + PLUSⅡfor

27、CPLD / FPGA design. MAX + PLUSⅡalso includes</p><p>　?、?Enter the text editor: MAX + PLUSⅡtext input language and compiler system supports AHDL, VHDL language, VERILOG language of the three input methods. &l

28、t;/p><p>　　③ wave input: If you know the input, output waveform, the waveform input can also be used. </p><p>　?、?hybrid approach: MAX + PLUSⅡdesign and development environment for graphical design

29、 entry, text editing input, waveform editing input hybrid editing. To do: in graphics editing, wave form editing module by editing the text include "module name. Inc" or the use of Function (... ..) Return (...

30、.) Way call. Similarly, the text editing module input form can also be called when the graphics editor, AHDL compiler results can be used in the VHDL language, VHDL compiler of the results can also be ente</p><

31、;p>　　Altera's QuartusⅡis a comprehensive PLD development software to support the schematic, VHDL, Verilog HDL, and AHDL (Altera Hardware Description Language) and other design input forms, embedded devices, and in

32、tegrated its own simulator, you can complete the design input to complete the hardware configuration of the PLD design process. </p><p>　　QuartusⅡin the XP, Linux and Unix on the use, in addition to using th

33、e Tcl script to complete the design process, to provide a complete graphical user interface design. With running speed, unified interface, feature set, easy to use and so on. </p><p>　　Altera's QuartusⅡs

34、upport IP core, including the LPM / MegaFunction macro function module library, allowing users to take full advantage of sophisticated modules, simplifying the design complexity and speed up the design speed. Good for th

35、ird-party EDA tool support also allows the user to the various stages in the design process using the familiar third-party EDA tools. </p><p>　　In addition, QuartusⅡand DSP Builder tools and by Matlab / Simu

36、link combination, you can easily achieve a variety of DSP applications; support Altera's programmable system chip (SOPC) development, set system-level design, embedded software development, programmable logic design

37、in one, is a comprehensive development platform. </p><p>　　MaxPLUSⅡgeneration as Altera's PLD design software, due to its excellent ease of use has been widely used. Altera has now stopped MaxPLUSⅡupdate

38、 support, QuartusⅡnot only support the device type as compared to the rich and the graphical interface changes. Altera QuartusⅡincluded in many such SignalTapⅡ, Chip Editor and RTL Viewer design aids, integrated SOPC and

39、 HardCopy design process, and inherit MaxPLUSⅡfriendly graphical interface and easy to use. </p><p>　　MaxPLUSⅡgeneration as Altera's PLD design software, due to its excellent ease of use has been widely

40、used. Altera has now stopped MaxPLUSⅡupdate support, QuartusⅡnot only support the device type as compared to the rich and the graphical interface changes. Altera QuartusⅡincluded in many such SignalTapⅡ, Chip Editor and

41、RTL Viewer design aids, integrated SOPC and HardCopy design process, and inherit MaxPLUSⅡ friendly graphical interface and easy to use. </p><p>　　Altera QuartusⅡ as a programmable logic design environment, d

42、ue to its strong design capabilities and intuitive interface, more and more digital systems designers welcome. </p><p>　　Altera's QuartusⅡis the fourth generation of programmable logic PLD software devel

43、opment platform. The platform supports a working group under the design requirements, including support for Internet-based collaborative design. Quartus platform and Cadence, ExemplarLogic, MentorGraphics, Synopsys and S

44、ynplicity EDA vendors and other development tools are compatible. LogicLock improve the software module design features, added FastFit compiler options, and promote the network editing performance, </p><p>　

45、　3. Development of language VHDL </p><p>　　VHDL (Very High Speed ??Integrated Circuit Hardware Description Language) is a very high speed integrated circuit hardware description language, it can describe the

46、 function of the hardware circuitry, signal connectivity and the time between languages. It can be more effective than the circuit diagram to express the characteristics of the hardware circuit. Using the VHDL language,

47、you can proceed to the general requirements of the system, since the detailed content will be designed to come down </p><p>　　VHDL, the main features are: </p><p>　?、?powerful, high flexibility:

48、 VHDL language is a powerful language structure, clear and concise code can be used to design complex control logic. VHDL language also supports hierarchical design, support design databases and build reusable components

49、. Currently, VHDL language has become a design, simulation, synthesis of standard hardware description language. </p><p>　　② Device independence: VHDL language allows designers to generate a design do not ne

50、ed to first select a specific device. For the same design description, you can use a variety of different device structures to achieve its function. So the design description stage, able to focus on design ideas. When th

51、e design, simulation, after the adoption of a specific device specified integrated, adapter can be. </p><p>　?、?Portability: VHDL language is a standard language, so the use of VHDL design can be carried out

52、 by different EDA tool support. Transplanted from one to another simulation tools simulation tools, synthesis tools from a port to another integrated tool, from a working platform into another working platform. EDA tools

53、 used in a technical skills, in other tools can also be used. </p><p>　?、?top-down design methods: the traditional design approach is bottom-up design or flat design. Bottom-up design methodology is to start

54、 the bottom of the module design, the gradual formation of the functional modules of complex circuits. Advantage of this design is obvious because it is a hierarchical circuit design, the general circuit sub-module are i

55、n accordance with the structure or function of division, so the circuit level clear, clear structure, easy people to develop, while the design ar</p><p>　?、?rich data types: as a hardware description languag

56、e VHDL data types are very rich language, in addition to VHDL language itself dozens of predefined data types, in the VHDL language programming also can be user-defined data types. Std_logic data types in particular the

57、use of VHDL language can make the most realistic complex signals in analog circuits. </p><p>　?、?modeling convenience: the VHDL language can be integrated in the statement and the statement are available for

58、 simulation, behavior description ability, therefore particularly suitable for signal modeling language VHDL. The current VHDL synthesizer to complex arithmetic comprehensive descriptions (such as: Quartus Ⅱ 2.0 and abov

59、e versions of std_logic_vector type of data can add, subtract, multiply, divide), so the circuit modeling for complex simulation of VHDL language, whether or comprehens</p><p>　　⑦ rich runtime and packages:

60、The current package supports VHDL, very rich, mostly in the form of libraries stored in a specific directory, the user can at any time. Such as the IEEE library collection std_logic_1164, std_logic_arith, std_logic_unsig

61、ned other package. In the CPLD / FPGA synthesis, EDA software vendors can also use the various libraries and provide package. VHDL language and the user using a variety of results can be stored in a library, in the desig

62、n of the follow-up can continue</p><p>　?、?VHDL language is a modeling hardware description language, so with ordinary computer languages ??are very different, common computer language is the CPU clock accor

63、ding to the beat, after an instruction to perform the next instruction, so instruction is a sequential, that is the order of execution, and execution of each instruction takes a specific time. VHDL language to describe t

64、he results with the corresponding hardware circuit, which follows the characteristics of hardware, there is no ord</p><p><b>　　EDA技術(shù)及軟件</b></p><p>　　EDA是電子設(shè)計(jì)自動(dòng)化(Electronic Design Aut

65、omation)的縮寫,在20世紀(jì)90年代初從計(jì)算機(jī)輔助設(shè)計(jì)(CAD)、計(jì)算機(jī)輔助制造(CAM)、計(jì)算機(jī)輔助測(cè)試(CAT)和計(jì)算機(jī)輔助工程(CAE)的概念發(fā)展而來。</p><p>　　EDA技術(shù)就是以計(jì)算機(jī)為工具，設(shè)計(jì)者在EDA軟件平臺(tái)上，用硬件描述語(yǔ)言HDL完成設(shè)計(jì)文件，然后由計(jì)算機(jī)自動(dòng)地完成邏輯編譯、化簡(jiǎn)、分割、綜合、優(yōu)化、布局、布線和仿真，直至對(duì)于特定目標(biāo)芯片的適配編譯、邏輯映射和編程下載等工作。<

66、/p><p>　　1 EDA技術(shù)的概念 </p><p>　　EDA技術(shù)是在電子CAD技術(shù)基礎(chǔ)上發(fā)展起來的計(jì)算機(jī)軟件系統(tǒng)，是指以計(jì)算機(jī)為工作平臺(tái)，融合了應(yīng)用電子技術(shù)、計(jì)算機(jī)技術(shù)、信息處理及智能化技術(shù)的最新成果，進(jìn)行電子產(chǎn)品的自動(dòng)設(shè)計(jì)。 </p><p>　　利用EDA工具，電子設(shè)計(jì)師可以從概念、算法、協(xié)議等開始設(shè)計(jì)電子系統(tǒng)，大量工作可以通過計(jì)算機(jī)完成，并可以將電子產(chǎn)品從

67、電路設(shè)計(jì)、性能分析到設(shè)計(jì)出IC版圖或PCB版圖的整個(gè)過程的計(jì)算機(jī)上自動(dòng)處理完成。 </p><p>　　現(xiàn)在對(duì)EDA的概念或范疇用得很寬。包括在機(jī)械、電子、通信、航空航天、化工、礦產(chǎn)、生物、醫(yī)學(xué)、軍事等各個(gè)領(lǐng)域，都有EDA的應(yīng)用。目前EDA技術(shù)已在各大公司、企事業(yè)單位和科研教學(xué)部門廣泛使用。例如在飛機(jī)制造過程中，從設(shè)計(jì)、性能測(cè)試及特性分析直到飛行模擬，都可能涉及到EDA技術(shù)。本文所指的EDA技術(shù)，主要針對(duì)電子電路

68、設(shè)計(jì)、PCB設(shè)計(jì)和IC設(shè)計(jì)。 </p><p>　　EDA設(shè)計(jì)可分為系統(tǒng)級(jí)、電路級(jí)和物理實(shí)現(xiàn)級(jí)。</p><p>　　2開發(fā)環(huán)境MAX+PLUSⅡ/QUARTERⅡ</p><p>　　Altera公司是世界三大CPLD／FPGA 廠家之一，它的器件能達(dá)到最高的性能和集成度，不僅僅因?yàn)椴捎昧讼冗M(jìn)的工藝和全新的邏輯結(jié)構(gòu)，還在于它提供了現(xiàn)代化的設(shè)計(jì)工具一MAX+PLUS

69、Ⅱ可編程邏輯開發(fā)軟件，該軟件是Altera公司推出的第三代PLD 開發(fā)系統(tǒng)。提供了一種與結(jié)構(gòu)無關(guān)的設(shè)計(jì)環(huán)境，使Altera CPLD 設(shè)計(jì)者能方便地進(jìn)行設(shè)計(jì)輸入、快速處理和器件編程。MAX+PLUSⅡ提供了全面的邏輯設(shè)計(jì)能力，包括電路圖、文本和波形的設(shè)計(jì)輸入以及編譯、邏輯綜合、仿真和定時(shí)分析以及器件編程等諸多功能。特別是在原理圖輸入等方面，MAX+PLUSⅡ被公認(rèn)為是最易使用、人機(jī)界面最友好的PLD 開發(fā)軟件。MAX+PLUSⅡ可以開發(fā)

70、除APEX20K 以外的任何CPLD／FPGA。</p><p>　　MAX+PLUSⅡ開發(fā)系統(tǒng)具有很多突出的特點(diǎn):</p><p><b>　?、匍_放式的界面。</b></p><p>　　②設(shè)計(jì)與結(jié)構(gòu)無關(guān)：MAX+PLUSⅡ支持Altera公司的Classic、ACEX 1K、MAX 3000、MAX 5000、MAX 7000、MAX 9

71、000、FLEX 6000、FLEX 8000和FLEX 10K等系列可編程邏輯器件，門數(shù)為600～250 000門，提供了業(yè)界真正與結(jié)構(gòu)無關(guān)的可編程邏輯設(shè)計(jì)環(huán)境。MAX+PLUSⅡ的編譯器還提供了強(qiáng)大的邏輯綜合與優(yōu)化功能以減輕用戶的設(shè)計(jì)負(fù)擔(dān)。</p><p>　?、劭稍诙喾N平臺(tái)運(yùn)行：MAX+PLUSⅡ軟件可在基于PC機(jī)的WindowsNT 4.0、Windows 98、Win dows 2000操作系統(tǒng)下運(yùn)行，

72、也可在Sun SPARCstations、HP 9000 Series 700/800、IBM RISC System/6000等工作站上運(yùn)行。</p><p>　?、芡耆苫篗AX+PLUSⅡ軟件的設(shè)計(jì)輸入、處理、校驗(yàn)功能完全集成于可編程邏輯開發(fā)工具內(nèi)，從而可以更快地進(jìn)行調(diào)試，縮短開發(fā)周期。</p><p>　?、菽K化工具：設(shè)計(jì)者可以從各種設(shè)計(jì)輸入、編輯、校驗(yàn)及器件編程工具中作出選

73、擇，形成用戶風(fēng)格的開發(fā)環(huán)境，必要時(shí)還可在保留原始功能的基礎(chǔ)上添加新的功能。由于MAX+PLUSⅡ支持多種器件系列，設(shè)計(jì)者無需學(xué)習(xí)新的開發(fā)工具即可對(duì)新結(jié)構(gòu)的器件進(jìn)行開發(fā)。</p><p>　?、拗С粥]件描述語(yǔ)言（HDL）：MAX+PLUSⅡ軟件支持多種HDL的設(shè)計(jì)輸入，包括標(biāo)準(zhǔn)的VHDL、Verilog HDL及Altera公司自己開發(fā)的硬件描述語(yǔ)言AHDL。</p><p>　?、?Meg

74、aCore功能：MegaCore 是經(jīng)過預(yù)先校驗(yàn)的為實(shí)現(xiàn)復(fù)雜的系統(tǒng)級(jí)功能而提供的HDL網(wǎng)表文件。它為ACEX 1K、MAX 7000、MAX 9000、FLEX 6000、FLEX 8000和FLEX 10K系列器件提供了最優(yōu)化設(shè)計(jì)。用戶可從Altera公司購(gòu)買這些MegaCore，使用它們可以減輕設(shè) 計(jì)任務(wù)，使設(shè)計(jì)者能將更多的時(shí)間和精力投入到改進(jìn)設(shè)計(jì)和最終產(chǎn)品上去。</p><p>　?、郞penCore特點(diǎn)：

75、MAX+PLUSⅡ軟件具有開放性內(nèi)核的特點(diǎn)，OpenCore可供設(shè)計(jì)者在購(gòu)買產(chǎn)品前來對(duì)自己的設(shè)計(jì)進(jìn)行評(píng)估。</p><p>　　同時(shí)，MAX+PLUSⅡ還有多種設(shè)計(jì)輸入方法，主要包括：</p><p>　?、賵D形設(shè)計(jì)輸入：MAX+PLUSⅡ的圖形設(shè)計(jì)輸入是較其他軟件更容易使用的特點(diǎn)，因?yàn)镸AX+PLUSⅡ提供了豐富的庫(kù)單元供設(shè)計(jì)者調(diào)用，尤其是在MAX2LIB里提供的mf庫(kù)幾乎包含了所有的7

76、4系列的器件，在prim庫(kù)里提供了數(shù)字電路中所有的分離器件。因此只要具有數(shù)字電路的知識(shí)，幾乎不需要過多的學(xué)習(xí)就可以利用MAX+PLUSⅡ進(jìn)行CPLD/FPGA的設(shè)計(jì)。MAX+PLUSⅡ還包括多種特殊的邏輯宏功能（Macro—Function）以及新型的參數(shù)化的兆功能（Mega—Function）模塊。充分利用這些模塊進(jìn)行設(shè)計(jì)，可以大大減輕設(shè)計(jì)人員的工作量和成倍地縮短設(shè)計(jì)周期。</p><p>　?、谖谋揪庉嬢斎耄?/p>

77、MAX+PLUSⅡ的文本輸入和編譯系統(tǒng)支持AHDL語(yǔ)言、VHDL語(yǔ)言、VERILOG語(yǔ)言三種輸入方式。</p><p>　　③波形輸入方式：如果知道輸入、輸出波形，也可以采用波形輸入方式。</p><p>　?、芑旌陷斎敕绞剑篗AX+PLUSⅡ設(shè)計(jì)開發(fā)環(huán)境，可以進(jìn)行圖形設(shè)計(jì)輸入、文本編輯輸入、波形編輯輸入混合編輯。具體操作方法是：在圖形編輯、波形編輯時(shí)形成模塊，在文本編輯時(shí)通過includ

78、e“模塊名.inc”或者采用Function（…..） Return(….)的方式進(jìn)行調(diào)用。同樣，文本編輯輸入形成的模塊，也可以在圖形編輯時(shí)調(diào)用，AHDL語(yǔ)言編譯的結(jié)果可以在VHDL 語(yǔ)言下使用，VHDL語(yǔ)言編譯的結(jié)果也可以在AHDL語(yǔ)言或圖形輸入時(shí)使用。這樣靈活多變的輸入方式，給設(shè)計(jì)使用者帶來了極大的方便。</p><p>　　QuartusⅡ是Altera公司的綜合性PLD開發(fā)軟件，支持原理圖、VHDL、Ve

79、rilog HDL以及AHDL（Altera Hardware Description Language）等多種設(shè)計(jì)輸入形式，內(nèi)嵌自有的綜合器以及仿真器，可以完成從設(shè)計(jì)輸入到硬件配置的完整PLD設(shè)計(jì)流程。</p><p>　　QuartusⅡ可以在XP、Linux以及Unix上使用，除了可以使用Tcl腳本完成設(shè)計(jì)流程外，提供了完善的用戶圖形界面設(shè)計(jì)方式。具有運(yùn)行速度快，界面統(tǒng)一，功能集中，易學(xué)易用等特點(diǎn)。<

80、/p><p>　　QuartusⅡ支持Altera的IP核，包含了LPM/MegaFunction宏功能模塊庫(kù)，使用戶可以充分利用成熟的模塊，簡(jiǎn)化了設(shè)計(jì)的復(fù)雜性、加快了設(shè)計(jì)速度。對(duì)第三方EDA工具的良好支持也使用戶可以在設(shè)計(jì)流程的各個(gè)階段使用熟悉的第三方EDA工具。</p><p>　　此外，QuartusⅡ通過和DSP Builder工具與Matlab/Simulink相結(jié)合，可以方便地實(shí)現(xiàn)

81、各種DSP應(yīng)用系統(tǒng)；支持Altera的片上可編程系統(tǒng)（SOPC）開發(fā)，集系統(tǒng)級(jí)設(shè)計(jì)、嵌入式軟件開發(fā)、可編程邏輯設(shè)計(jì)于一體，是一種綜合性的開發(fā)平臺(tái)。</p><p>　　MaxPLUSⅡ作為Altera的上一代PLD設(shè)計(jì)軟件，由于其出色的易用性而得到了廣泛的應(yīng)用。目前Altera已經(jīng)停止了對(duì)MaxPLUSⅡ的更新支持，QuartusⅡ與之相比不僅僅是支持器件類型的豐富和圖形界面的改變。Altera在QuartusⅡ

82、中包含了許多諸如SignalTapⅡ、Chip Editor和RTL Viewer的設(shè)計(jì)輔助工具，集成了SOPC和HardCopy設(shè)計(jì)流程，并且繼承了MaxPLUSⅡ友好的圖形界面及簡(jiǎn)便的使用方法。</p><p>　　MaxPLUSⅡ作為Altera的上一代PLD設(shè)計(jì)軟件，由于其出色的易用性而得到了廣泛的應(yīng)用。目前Altera已經(jīng)停止了對(duì)MaxPLUS Ⅱ的更新支持，QuartusⅡ與之相比不僅僅是支持器件類型

83、的豐富和圖形界面的改變。Altera在QuartusⅡ中包含了許多諸如SignalTapⅡ、Chip Editor和RTL Viewer的設(shè)計(jì)輔助工具，集成了SOPC和HardCopy設(shè)計(jì)流程，并且繼承了MaxPLUSⅡ友好的圖形界面及簡(jiǎn)便的使用方法。</p><p>　　Altera QuartusⅡ作為一種可編程邏輯的設(shè)計(jì)環(huán)境, 由于其強(qiáng)大的設(shè)計(jì)能力和直觀易用的接口，越來越受到數(shù)字系統(tǒng)設(shè)計(jì)者的歡迎。</

84、p><p>　　Altera的QuartusⅡ可編程邏輯軟件屬于第四代PLD開發(fā)平臺(tái)。該平臺(tái)支持一個(gè)工作組環(huán)境下的設(shè)計(jì)要求，其中包括支持基于Internet的協(xié)作設(shè)計(jì)。Quartus平臺(tái)與Cadence、ExemplarLogic、 MentorGraphics、Synopsys和Synplicity等EDA供應(yīng)商的開發(fā)工具相兼容。改進(jìn)了軟件的LogicLock模塊設(shè)計(jì)功能，增添 了FastFit編譯選項(xiàng)，推進(jìn)了網(wǎng)絡(luò)

85、編輯性能，而且提升了調(diào)試能力。支持MAX7000/MAX3000等乘積項(xiàng)器件。</p><p><b>　　3開發(fā)語(yǔ)言VHDL</b></p><p>　　VHDL(Very High Speed Integrated Circuit Hardware Description Language)是非常高速集成電路硬件描述語(yǔ)言，是可以描述硬件電路的功能、信號(hào)連接關(guān)系及定

86、時(shí)關(guān)系的語(yǔ)言．它能比電路原理圖更有效地表示硬件電路的特性。使用VHDL語(yǔ)言，可以就系統(tǒng)的總體要求出發(fā)，自上至下地將設(shè)計(jì)內(nèi)容細(xì)化，最后完成系統(tǒng)硬件的整體設(shè)計(jì)。VHDL語(yǔ)言已作為一種IEEE的工業(yè)標(biāo)準(zhǔn)，設(shè)計(jì)結(jié)果便于復(fù)用和交流。目前，它還不能應(yīng)用于模擬電路的設(shè)計(jì)，但已有人投入研究。VHDL程序結(jié)構(gòu)包括：實(shí)體(Entity)、結(jié)構(gòu)體(Architecture)、配置(Configuration)、包集合(Package)及庫(kù)(Library)。

87、其中，實(shí)體是一個(gè)VHDL程序的基本單元，由實(shí)體說明和結(jié)構(gòu)體兩部分組成：實(shí)體說明用于描述設(shè)計(jì)系統(tǒng)的外部接口信號(hào)；結(jié)構(gòu)體用于描述系統(tǒng)的行為、系統(tǒng)數(shù)據(jù)的流程或系統(tǒng)組織結(jié)構(gòu)形式。配置用語(yǔ)從庫(kù)中選取所需的單元來組成系統(tǒng)設(shè)計(jì)的不同規(guī)格的不同版本，使被設(shè)計(jì)系統(tǒng)的功能發(fā)生變化。包集合存放各設(shè)計(jì)模塊能共享的數(shù)據(jù)類型、常數(shù)、子程序等。庫(kù)用于存放已編譯的實(shí)體、構(gòu)造體</p><p>　　VHDL語(yǔ)言的主要特點(diǎn)是：</p>

88、<p>　　①功能強(qiáng)大，靈活性高：VHDL語(yǔ)言是一種功能強(qiáng)大的語(yǔ)言結(jié)構(gòu)，可用簡(jiǎn)潔明確的代碼來進(jìn)行復(fù)雜控制邏輯的設(shè)計(jì)。同時(shí)VHDL語(yǔ)言還支持層次化的設(shè)計(jì)，支持設(shè)計(jì)庫(kù)和可重復(fù)使用的元件生成。目前，VHDL語(yǔ)言已成為一種設(shè)計(jì)、仿真、綜合的標(biāo)準(zhǔn)硬件描述語(yǔ)言。</p><p>　?、谄骷o關(guān)性：VHDL語(yǔ)言允許設(shè)計(jì)者在生成一個(gè)設(shè)計(jì)時(shí)不需要首先選擇一個(gè)具體的器件。對(duì)于同一個(gè)設(shè)計(jì)描述，可以采用多種不同器件結(jié)構(gòu)來實(shí)現(xiàn)

89、其功能。因此設(shè)計(jì)描述階段，可以集中精力從事設(shè)計(jì)構(gòu)思。當(dāng)設(shè)計(jì)、仿真通過后，指定具體的器件綜合、適配即可。</p><p>　?、劭梢浦残裕篤HDL語(yǔ)言是一種標(biāo)準(zhǔn)的語(yǔ)言，故采用VHDL進(jìn)行的設(shè)計(jì)可以被不同的EDA工具所支持。從一個(gè)仿真工具移植到另一個(gè)仿真工具，從一個(gè)綜合工具移植到另一個(gè)綜合工具，從一個(gè)工作平臺(tái)移植到另一個(gè)工作平臺(tái)。在一個(gè)EDA工具中采用的技術(shù)技巧，在其它工具中同樣可以采用。</p>&l

90、t;p>　?、茏皂斚蛳碌脑O(shè)計(jì)方法：傳統(tǒng)的設(shè)計(jì)方法是，自底向上的設(shè)計(jì)或平坦式設(shè)計(jì)。自底向上的設(shè)計(jì)方法是先從底層模塊設(shè)計(jì)開始，逐漸由各個(gè)模塊形成功能復(fù)雜的電路。這種設(shè)計(jì)方法優(yōu)點(diǎn)是很明顯的，因?yàn)樗且环N層次設(shè)計(jì)電路，一般電路的子模塊都是按照結(jié)構(gòu)或功能劃分，因此這種電路層次清楚，結(jié)構(gòu)明確，便于多人合作開發(fā)，同時(shí)設(shè)計(jì)文件易于存檔，易于交流。自底向上設(shè)計(jì)方法的缺點(diǎn)也很明顯，往往由于整體設(shè)計(jì)思路不對(duì)而使的花費(fèi)幾個(gè)月的低層設(shè)計(jì)付之東流。平坦式設(shè)計(jì)

91、是整個(gè)電路只含有一個(gè)模塊，電路的設(shè)計(jì)是平鋪直敘的，沒有結(jié)構(gòu)和功能上的劃分，因此不是層次電路的設(shè)計(jì)方式。優(yōu)點(diǎn)是小型電路設(shè)計(jì)時(shí)可以節(jié)省時(shí)間和精力，但隨著電路復(fù)雜程度的增加，這種設(shè)計(jì)方式的缺點(diǎn)變的異常突出。自頂向下的設(shè)計(jì)方法是將要設(shè)計(jì)的電路進(jìn)行最頂層的描述（頂層建模），然后利用EDA軟件進(jìn)行頂層仿真，如果頂層設(shè)計(jì)的仿真結(jié)果滿足要求，則可以繼續(xù)將頂層劃分的模塊進(jìn)行低一級(jí)的劃分并仿真，這樣一級(jí)一級(jí)設(shè)計(jì)最終將完成整個(gè)電路的設(shè)計(jì)。自頂向下的設(shè)計(jì)方法與

92、前面兩種方法相比優(yōu)點(diǎn)是很明顯的。</p><p>　?、輸?shù)據(jù)類型豐富：作為硬件描述語(yǔ)言的一種VHDL語(yǔ)言的數(shù)據(jù)類型非常豐富，除了VHDL語(yǔ)言自身預(yù)定義的十種數(shù)據(jù)類型外，在VHDL語(yǔ)言程序設(shè)計(jì)中還可以由用戶自定義數(shù)據(jù)類型。特別是std_logic數(shù)據(jù)類型的使用，使得VHDL語(yǔ)言能最真實(shí)模擬電路中的復(fù)雜信號(hào)。</p><p>　?、藿７奖悖河捎赩HDL語(yǔ)言中可綜合的語(yǔ)句和用于仿真的語(yǔ)句齊備，

93、行為描述能力強(qiáng)，因此VHDL語(yǔ)言特別適合信號(hào)建模。目前VHDL的綜合器能對(duì)復(fù)雜的算術(shù)描述進(jìn)行綜合（如：QuartusⅡ 2.0以上的版本都能對(duì)std_logic_vector類型的數(shù)據(jù)進(jìn)行加、減、乘、除），因此對(duì)于復(fù)雜電路的建模VHDL語(yǔ)言無論仿真還是綜合都是非常合適的描述語(yǔ)言。</p><p>　?、哌\(yùn)行庫(kù)和程序包豐富：目前支持VHDL語(yǔ)言的程序包很豐富，大多以庫(kù)的形式存放在特定的目錄下，用戶可隨時(shí)調(diào)用。如IE

94、EE庫(kù)收集了std_logic_1164、std_logic_arith、std_logic_unsigned等程序包。在CPLD/FPGA綜合時(shí)，還可以使用EDA軟件商提供的各種庫(kù)和程序包。而且用戶利用VHDL語(yǔ)言編寫的各種成果都可以以庫(kù)的形式存放，在后續(xù)的設(shè)計(jì)中可以繼續(xù)使用。</p><p>　?、?VHDL語(yǔ)言是一種硬件電路的建模描述語(yǔ)言，因此與普通的計(jì)算機(jī)語(yǔ)言有較大差別，普通計(jì)算機(jī)語(yǔ)言是CPU按照時(shí)鐘的節(jié)