1.2umeeprom低電壓下工作的失效分析與工藝優(yōu)化

1、 上海交通大學(xué)工程碩士學(xué)位論文 1.2um EEPROM 低電壓下工作的失效分析與工藝優(yōu)化 1.2um EEPROM 低電壓下工作的失效分析與工藝優(yōu)化 碩士姓名：錢國平 專 業(yè)：軟件工程 學(xué) 號：1042102084 導(dǎo) 師：程秀蘭 副教授 上海交通大學(xué)微電子學(xué)院 2007 年 1 月 1.2UM EEPROM LOW VOLTAGE FAILURE ANALYSIS AND PROCESS OPTIMIZATIO

2、N ABSTRACT As the portable electronic products are developing rapidly, low power consumption EEPROM design has been a popular field. In this paper, a product fabricated by the mature technology of 1.2um EEPROM process is

3、 introduced. To achieve the target of low power consumption, the designer modified the circuit’s layout. However, the pilot wafers made by the primary process failed severely under low voltage testing condition. Firstl

4、y, we collected and analyzed a mass of PVM data to investigate the root cause of low voltage failure. Then, the circuit’s failure mechanism was discussed theoretically. We studied the theories including the influence of

5、floating-gate to EEPROM memory cells, the relationship between erase/write characteristics and Fowler-Nordheim tunneling mechanism, the working principle of the charge pump in a high voltage generator, the influence of k

6、ey process parameters to the circuit, the relationship between failure and threshold voltage of POLY1 NMOS, and so on. Following the above analysis, we proposed a solution to solve the problem by optimizing some process

7、parameter. To modify the process parameter, we did numerous process and device simulation with the TCAD software. On the basis of the simulation results, some splits were arranged correctly and the appropriate optimizing